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tensorflow/compiler/mlir/tensorflow/tests/strip_tf_attributes.mlir
// CHECK-NOT: tf func.func @strips_attributes(%arg0: tensor<32x28x28x1xf32> {tf._user_specified_name = "x"}, %arg1: tensor<3x3x1x5xf32> {tf._user_specified_name = "w1"}, %arg2: tensor<5xf32> {tf._user_specified_name = "b1"}, %arg3: tensor<3920x10xf32> {tf._user_specified_name = "w2"},
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Oct 25 20:04:10 UTC 2022 - 1.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/stablehlo/tests/passes/restore_function_name.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Feb 08 22:40:14 UTC 2024 - 3.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/386Ops.go
{name: "SUBLloadidx4", argLength: 4, reg: gp21loadidx, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+arg2*4+auxint+aux, arg3 = mem
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 14 08:10:32 UTC 2023 - 45.1K bytes - Viewed (0) -
fess-crawler/src/main/java/org/codelibs/fess/crawler/client/http/ntlm/SmbjEngine.java
@Override public String generateType1Msg(final String arg0, final String arg1) throws NTLMEngineException { // TODO Auto-generated method stub return null; } @Override public String generateType3Msg(final String arg0, final String arg1, final String arg2, final String arg3, final String arg4) throws NTLMEngineException { // TODO Auto-generated method stub
Registered: Wed Jun 12 15:17:51 UTC 2024 - Last Modified: Thu Feb 22 01:36:27 UTC 2024 - 1.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tpu_partitioned_op_conversion.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Jan 20 17:43:51 UTC 2023 - 8.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/fuse_tpu_compile_and_execute_ops.mlir
func.func private @test_fuse_dynamic_dimension_ops(%arg0: tensor<?x?xi32>, %arg1: tensor<*x!tf_type.resource>, %arg2: tensor<2xi64>, %arg3: tensor<?xi64>, %arg4: tensor<?xi64>) -> tensor<*xi32> { // CHECK-NOT: tf._TPUCompileMlirOp // CHECK-NOT: tf.TPUCompileSucceededAssert // CHECK-NOT: tf.TPUExecuteOp // CHECK-NOT: tf.SetStaticDimensionBounds // CHECK: [[read_result:%.*]] = "tf.ReadVariableOp"(%arg1)
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 13.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/while_op.mlir
func.func @main(%arg0: tensor<i32>, %arg1: tensor<1xf32>) -> tensor<1xf32> { // While %arg0 is greater than zero, element wise add %arg1 with itself. %0:2 = "tfl.while"(%arg0, %arg1) ({ ^bb0(%arg2: tensor<*xi32>, %arg3: tensor<*xf32>): %1 = func.call @cond(%arg2, %arg3) : (tensor<*xi32>, tensor<*xf32>) -> tensor<i1> "tfl.yield"(%1) : (tensor<i1>) -> () }, { ^bb0(%arg2: tensor<*xi32>, %arg3: tensor<*xf32>):
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Jul 14 16:41:28 UTC 2022 - 2K bytes - Viewed (0) -
src/crypto/md5/gen.go
{{end}} // round 1 {{range $i, $s := dup 4 .Shift1 -}} {{printf "arg0 = arg1 + bits.RotateLeft32((((arg2^arg3)&arg1)^arg3)+arg0+x%x+%#08x, %d)" (idx 1 $i) (index $.Table1 $i) $s | relabel}} {{rotate -}} {{end}} // round 2 {{range $i, $s := dup 4 .Shift2 -}} {{printf "arg0 = arg1 + bits.RotateLeft32((((arg1^arg2)&arg3)^arg2)+arg0+x%x+%#08x, %d)" (idx 2 $i) (index $.Table2 $i) $s | relabel}} {{rotate -}}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 13 18:57:38 UTC 2024 - 4.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
// unsigned arg0 >> arg2, shifting in bits from arg1 (==(arg1<<64+arg0)>>arg2, keeping low 64 bits), shift amount is mod 64 {name: "SHRDQ", argLength: 3, reg: gp31shift, asm: "SHRQ", resultInArg0: true, clobberFlags: true}, // unsigned arg0 << arg2, shifting in bits from arg1 (==(arg0<<64+arg1)<<arg2, keeping high 64 bits), shift amount is mod 64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2) {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2) {name: "MADD", argLength: 3, reg: gp31, asm: "MADD"}, // +arg0 + (arg1 * arg2) {name: "MADDW", argLength: 3, reg: gp31, asm: "MADDW"}, // +arg0 + (arg1 * arg2), 32-bit {name: "MSUB", argLength: 3, reg: gp31, asm: "MSUB"}, // +arg0 - (arg1 * arg2)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0)