// For example:
// (CMPBconstload c (ADDQ x y)) -> (CMPBconstloadidx1 c x y) -> (CMPB c (MOVBloadidx1 x y))

(CMP(Q|L|W|B)load {sym} [off] ptr x mem) => (CMP(Q|L|W|B) (MOV(Q|L|W|B)load {sym} [off] ptr mem) x)

(CMP(Q|L|W|B)constload {sym} [vo] ptr mem) && vo.Val() == 0 => (TEST(Q|L|W|B) x:(MOV(Q|L|W|B)load {sym} [vo.Off()] ptr mem) x)

(CMPQconstload {sym} [vo] ptr mem) && vo.Val() != 0 => (CMPQconst (MOVQload {sym} [vo.Off()] ptr mem) [vo.Val()])

TEXT ·RewindAndSetgid(SB),NOSPLIT|NOFRAME,$0-0
	// Rewind stack pointer so anything that happens on the stack
	// will clobber the test pattern created by the caller
	ADD	$(1024*8), X2

	// Ask signaller to setgid
	MOV	$1, X5
	FENCE
	MOVW	X5, ·Baton(SB)
	FENCE

	// Wait for setgid completion
loop:
	FENCE
	MOVW	·Baton(SB), X5
	OR	X6, X6, X6	// hint that we're in a spin loop
	BNE	ZERO, X5, loop
	FENCE

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// See the top of AMD64splitload.rules for discussion of these rules.

(CMP(L|W|B)load {sym} [off] ptr x mem) => (CMP(L|W|B) (MOV(L|W|B)load {sym} [off] ptr mem) x)

(CMPLconstload {sym} [vo] ptr mem) => (CMPLconst (MOVLload {sym} [vo.Off()] ptr mem) [vo.Val()])
(CMPWconstload {sym} [vo] ptr mem) => (CMPWconst (MOVWload {sym} [vo.Off()] ptr mem) [vo.Val16()])

	MOVL 2147483648(AX), AX  // 8b8000000080
	MOVL -2147483648(AX), AX // 8b8000000080
	ADDL 2147483648(AX), AX  // 038000000080
	ADDL -2147483648(AX), AX // 038000000080
	// Make sure MOV CR/DR continues to work after changing its movtabs.
	MOVL CR0, AX // 0f20c0
	MOVL CR0, DX // 0f20c2
	MOVL CR4, DI // 0f20e7
	MOVL AX, CR0 // 0f22c0
	MOVL DX, CR0 // 0f22c2
	MOVL DI, CR4 // 0f22e7
	MOVL DR0, AX // 0f21c0

		default:
			c.ctxt.Diag("unexpected branch encoding\n%v", p)
		}

	case 7: // mov r, soreg
		r := int(p.To.Reg)
		if r == 0 {
			r = int(o.param)
		}
		v := c.regoff(&p.To)
		o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))

	case 8: // mov soreg, r
		r := int(p.From.Reg)
		if r == 0 {
			r = int(o.param)
		}
		v := c.regoff(&p.From)

    protected def getAsmSource(String methodName) {
        if (toolChain.isVisualCpp()) {
            return """
.386
.model    flat

PUBLIC    _${methodName}
_TEXT     SEGMENT
_${methodName}    PROC
mov    eax, DWORD PTR 4[esp]
add    eax, DWORD PTR 8[esp]
ret    0
_${methodName}    ENDP
_TEXT   ENDS
END
"""
        }else{
            return """
.text
.globl  _${methodName}
_${methodName}:

	//            carry = hi
	//        }
	//        return carry + c1 + c2
	//    }
	//
	// The loop is fully unrolled and the hi / carry registers are alternated
	// instead of introducing a MOV.

	z = Mem{Base: Load(Param("z"), GP64())}
	x = Mem{Base: Load(Param("x"), GP64())}
	Load(Param("y"), RDX) // implicit source of MULXQ

	carry = GP64()
	XORQ(carry, carry) // zero out carry
	z0 := GP64()

	case "s390x":
		ill = append(ill[:0], 0xa7, 0x09, 0x00, 0x00)         // MOVD $0, R0
		ill = append(ill, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x24) // MOVD R0, (R0)
	case "riscv64":
		binary.LittleEndian.PutUint32(ill, 0x00003023) // MOV X0, (X0)
	default:
		// Just leave it as 0 and hope for the best.
	}

	f.x = uintptr(unsafe.Pointer(&ill[0]))
	p := &f
	fn := *(*func())(unsafe.Pointer(&p))
	syncIcache(f.x)
	fn()

	/*1727*/ uint16(xReadSlashR),
	/*1728*/ uint16(xArgCR0dashCR7),
	/*1729*/ uint16(xArgRmf32),
	/*1730*/ uint16(xMatch),
	/*1731*/ uint16(xSetOp), uint16(MOV),
	/*1733*/ uint16(xReadSlashR),
	/*1734*/ uint16(xArgCR0dashCR7),
	/*1735*/ uint16(xArgRmf64),
	/*1736*/ uint16(xMatch),
	/*1737*/ uint16(xCondIs64), 1740, 1746,
	/*1740*/ uint16(xSetOp), uint16(MOV),
	/*1742*/ uint16(xReadSlashR),

introduced, for example, by the compiler's optimization passes.

Any given line of Go code could get assigned more instructions than it
may appear from reading the source. In particular, matching all MOV
instructions should be avoided; the compiler may add them for
unrelated reasons and this may render the test ineffective.

-- Line matching logic

Regexps are always matched from the start of the instructions line.