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Results 61 - 70 of 80 for fmadd (0.49 sec)

  1. src/cmd/asm/internal/asm/testdata/arm64.s

    	VUMIN	V3.S2, V2.S2, V1.S2             // 416ca32e
    	VUMIN	V3.S4, V2.S4, V1.S4             // 416ca36e
    	FCCMPS	LT, F1, F2, $1	                // 41b4211e
    	FMADDS	F1, F3, F2, F4                  // 440c011f
    	FMADDD	F4, F5, F4, F4                  // 8414441f
    	FMSUBS	F13, F21, F13, F19              // b3d50d1f
    	FMSUBD	F11, F7, F15, F31               // ff9d4b1f
    	FNMADDS	F1, F3, F2, F4                  // 440c211f
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
    - Viewed (0)
  2. src/cmd/vendor/golang.org/x/arch/x86/x86asm/tables.go

    	FDECSTP:         "FDECSTP",
    	FDIV:            "FDIV",
    	FDIVP:           "FDIVP",
    	FDIVR:           "FDIVR",
    	FDIVRP:          "FDIVRP",
    	FFREE:           "FFREE",
    	FFREEP:          "FFREEP",
    	FIADD:           "FIADD",
    	FICOM:           "FICOM",
    	FICOMP:          "FICOMP",
    	FIDIV:           "FIDIV",
    	FIDIVR:          "FIDIVR",
    	FILD:            "FILD",
    	FIMUL:           "FIMUL",
    	FINCSTP:         "FINCSTP",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon May 16 22:24:28 UTC 2022
    - 266.8K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/ppc64/a.out.go

    	AEXTSH
    	AEXTSHCC
    	AFABS
    	AFABSCC
    	AFADD
    	AFADDCC
    	AFADDS
    	AFADDSCC
    	AFCMPO
    	AFCMPU
    	AFCTIW
    	AFCTIWCC
    	AFCTIWZ
    	AFCTIWZCC
    	AFDIV
    	AFDIVCC
    	AFDIVS
    	AFDIVSCC
    	AFMADD
    	AFMADDCC
    	AFMADDS
    	AFMADDSCC
    	AFMOVD
    	AFMOVDCC
    	AFMOVDU
    	AFMOVS
    	AFMOVSU
    	AFMOVSX
    	AFMOVSZ
    	AFMSUB
    	AFMSUBCC
    	AFMSUBS
    	AFMSUBSCC
    	AFMUL
    	AFMULCC
    	AFMULS
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/rewriteCond_test.go

    	{"SubShift32", testSubShift32},
    }
    
    var crBenches = []struct {
    	name string
    	bf   func(b *testing.B)
    }{
    	{"SoloJump", benchSoloJump},
    	{"CombJump", benchCombJump},
    }
    
    // Test int32/int64's add/sub/madd/msub operations with boundary values to
    // ensure the optimization to 'comparing to zero' expressions of if-statements
    // yield expected results.
    // 32 rewriting rules are covered. At least two scenarios for "Canonicalize
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 24 01:19:09 UTC 2023
    - 11.1K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewritePPC64.go

    		return true
    	}
    	return false
    }
    func rewriteValuePPC64_OpPPC64FADD(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (FADD (FMUL x y) z)
    	// cond: x.Block.Func.useFMA(v)
    	// result: (FMADD x y z)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			if v_0.Op != OpPPC64FMUL {
    				continue
    			}
    			_ = v_0.Args[1]
    			v_0_0 := v_0.Args[0]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/arm64/a.out.go

    	ALDORH
    	ALDORLB
    	ALDORLD
    	ALDORLH
    	ALDORLW
    	ALDORW
    	ALDP
    	ALDPSW
    	ALDPW
    	ALDXP
    	ALDXPW
    	ALDXR
    	ALDXRB
    	ALDXRH
    	ALDXRW
    	ALSL
    	ALSLW
    	ALSR
    	ALSRW
    	AMADD
    	AMADDW
    	AMNEG
    	AMNEGW
    	AMOVB
    	AMOVBU
    	AMOVD
    	AMOVH
    	AMOVHU
    	AMOVK
    	AMOVKW
    	AMOVN
    	AMOVNW
    	AMOVP
    	AMOVPD
    	AMOVPQ
    	AMOVPS
    	AMOVPSW
    	AMOVPW
    	AMOVW
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/mips/asm0.go

    			opset(AMOVH, r0)
    
    		case AMOVBU:
    			opset(AMOVHU, r0)
    
    		case AMUL:
    			opset(AREM, r0)
    			opset(AREMU, r0)
    			opset(ADIVU, r0)
    			opset(AMULU, r0)
    			opset(ADIV, r0)
    			opset(AMADD, r0)
    			opset(AMSUB, r0)
    
    		case AMULV:
    			opset(ADIVV, r0)
    			opset(ADIVVU, r0)
    			opset(AMULVU, r0)
    			opset(AREMV, r0)
    			opset(AREMVU, r0)
    
    		case ASLL:
    			opset(ASRL, r0)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 17:46:09 UTC 2024
    - 53.6K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    	}
    	return false
    }
    func rewriteValueRISCV64_OpRISCV64FADDD(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (FADDD a (FMULD x y))
    	// cond: a.Block.Func.useFMA(v)
    	// result: (FMADDD x y a)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			a := v_0
    			if v_1.Op != OpRISCV64FMULD {
    				continue
    			}
    			y := v_1.Args[1]
    			x := v_1.Args[0]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
  9. test/codegen/arithmetic.go

    	// arm:`MULA`,-`MUL\s`
    	// arm64:`MADDW`,-`MULW`
    	r0 := a*b + c
    	// arm:`MULA`,-`MUL\s`
    	// arm64:`MADDW`,-`MULW`
    	r1 := c*79 + a
    	// arm:`ADD`,-`MULA`,-`MUL\s`
    	// arm64:`ADD`,-`MADD`,-`MULW`
    	// ppc64x:`ADD`,-`MULLD`
    	r2 := b*64 + c
    	return r0, r1, r2
    }
    
    func MULS(a, b, c uint32) (uint32, uint32, uint32) {
    	// arm/7:`MULS`,-`MUL\s`
    	// arm/6:`SUB`,`MUL\s`,-`MULS`
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/loong64/asm.go

    	AAMCASB:    0x070B0 << 15, // amcas.b
    	AAMCASH:    0x070B1 << 15, // amcas.h
    	AAMCASW:    0x070B2 << 15, // amcas.w
    	AAMCASV:    0x070B3 << 15, // amcas.d
    	AAMADDW:    0x070C2 << 15, // amadd.w
    	AAMADDV:    0x070C3 << 15, // amadd.d
    	AAMANDW:    0x070C4 << 15, // amand.w
    	AAMANDV:    0x070C5 << 15, // amand.d
    	AAMORW:     0x070C6 << 15, // amor.w
    	AAMORV:     0x070C7 << 15, // amor.d
    	AAMXORW:    0x070C8 << 15, // amxor.w
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 61.8K bytes
    - Viewed (0)
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