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Results 61 - 70 of 83 for f64 (0.06 sec)

  1. src/math/big/floatconv_test.go

    		if test.prec == 53 && test.format != 'p' && f.Sign() != 0 && (test.round == ToNearestEven || test.round == defaultRound) {
    			f64, acc := f.Float64()
    			if acc != Exact {
    				t.Errorf("%v: expected exact conversion to float64", test)
    				continue
    			}
    			got := strconv.FormatFloat(f64, test.format, test.digits, 64)
    			if got != test.want {
    				t.Errorf("%v: got %s; want %s", test, got, test.want)
    			}
    		}
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Dec 13 18:45:54 UTC 2021
    - 24.3K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf_patterns.td

    include "mhlo/IR/hlo_ops.td"
    
    def SignedIntTensor : TensorOf<[I1, I8, I16, I32, I64]>;
    def UnsignedIntTensor : TensorOf<[UI8, UI16, UI32, UI64]>;
    
    // IEEE compliant floating point tensors.
    def IEEEFloatTensor : TensorOf<[F16, F32, F64]>;
    
    //===----------------------------------------------------------------------===//
    // BatchNorm op patterns.
    //===----------------------------------------------------------------------===//
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon May 06 18:46:23 UTC 2024
    - 34.8K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/transforms/while_loop_outline.cc

        return true;
      };
      return just_call(while_op.getBody()) && just_call(while_op.getCond());
    }
    
    bool IsCompatibleTypeWithTFLCastOp(Type type) {
      auto elemType = getElementTypeOrSelf(type);
      // F16, F32, F64, BF16 types are allowed.
      if (elemType.isBF16() || elemType.isF16() || elemType.isF32() ||
          elemType.isF64())
        return true;
    
      // I1, I4, I8, I16, I32, I64 types are allowed.
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 11.8K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/mips/obj0.go

    			p.From.Offset = 0
    		}
    
    	case AMOVD:
    		if p.From.Type == obj.TYPE_FCONST {
    			f64 := p.From.Val.(float64)
    			if math.Float64bits(f64) == 0 && c.ctxt.Arch.Family == sys.MIPS64 {
    				p.As = AMOVV
    				p.From.Type = obj.TYPE_REG
    				p.From.Reg = REGZERO
    				break
    			}
    			p.From.Type = obj.TYPE_MEM
    			p.From.Sym = ctxt.Float64Sym(f64)
    			p.From.Name = obj.NAME_EXTERN
    			p.From.Offset = 0
    		}
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 19:28:53 UTC 2023
    - 30.6K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/quantization/stablehlo/passes/bridge/convert_tf_quant_to_mhlo_int_test.cc

        // since it LiteralTestUtil asserts different integers even if it is within
        // error_spec.
        TF_ASSERT_OK_AND_ASSIGN(auto expected_double, expected->Convert(xla::F64))
        TF_ASSERT_OK_AND_ASSIGN(auto result_double, result->Convert(xla::F64))
        EXPECT_TRUE(xla::LiteralTestUtil::Near(expected_double, result_double,
                                               xla::ErrorSpec(error_tolerance)));
      }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Apr 03 01:03:21 UTC 2024
    - 35.8K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir

    }
    
    func.func @real(%arg0: tensor<1 x complex<f64>>) -> tensor<1xf64> {
      %0 = "tf.Real"(%arg0) : (tensor<1 x complex<f64>>) -> tensor<1xf64>
      func.return %0: tensor<1xf64>
    
    // CHECK-LABEL: real
    // CHECK:  "tfl.real"(%arg0) : (tensor<1xcomplex<f64>>) -> tensor<1xf64>
    // CHECK:  return
    }
    
    func.func @imag(%arg0: tensor<1 x complex<f64>>) -> tensor<1xf64> {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 05 01:54:33 UTC 2024
    - 153.4K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/ppc64/obj9.go

    			p.From.Offset = 0
    		}
    
    	case AFMOVD:
    		if p.From.Type == obj.TYPE_FCONST {
    			f64 := p.From.Val.(float64)
    			// Constant not needed in memory for float +/- 0
    			if f64 != 0 && !convertFMOVtoXXSPLTIDP(p) {
    				p.From.Type = obj.TYPE_MEM
    				p.From.Sym = ctxt.Float64Sym(f64)
    				p.From.Name = obj.NAME_EXTERN
    				p.From.Offset = 0
    			}
    		}
    
    	case AMOVW, AMOVWZ:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 40.8K bytes
    - Viewed (0)
  8. src/math/all_test.go

    		return true
    	case a == b:
    		return Signbit(a) == Signbit(b)
    	}
    	return false
    }
    
    func TestNaN(t *testing.T) {
    	f64 := NaN()
    	if f64 == f64 {
    		t.Fatalf("NaN() returns %g, expected NaN", f64)
    	}
    	f32 := float32(f64)
    	if f32 == f32 {
    		t.Fatalf("float32(NaN()) is %g, expected NaN", f32)
    	}
    }
    
    func TestAcos(t *testing.T) {
    	for i := 0; i < len(vf); i++ {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jul 07 17:39:26 UTC 2023
    - 86.8K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/sym.go

    		s.Set(AttrContentAddressable, true)
    		ctxt.constSyms = append(ctxt.constSyms, s)
    	})
    }
    
    func (ctxt *Link) Float64Sym(f float64) *LSym {
    	i := math.Float64bits(f)
    	name := fmt.Sprintf("$f64.%016x", i)
    	return ctxt.LookupInit(name, func(s *LSym) {
    		s.Size = 8
    		s.WriteFloat64(ctxt, 0, f)
    		s.Type = objabi.SRODATA
    		s.Set(AttrLocal, true)
    		s.Set(AttrContentAddressable, true)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 14:41:10 UTC 2024
    - 14.1K bytes
    - Viewed (0)
  10. src/cmd/internal/obj/wasm/wasmobj.go

    	i64 valueType = 0x7E
    	f32 valueType = 0x7D
    	f64 valueType = 0x7C
    )
    
    func regType(reg int16) valueType {
    	switch {
    	case reg == REG_SP:
    		return i32
    	case reg >= REG_R0 && reg <= REG_R15:
    		return i64
    	case reg >= REG_F0 && reg <= REG_F15:
    		return f32
    	case reg >= REG_F16 && reg <= REG_F31:
    		return f64
    	default:
    		panic("invalid register")
    	}
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jun 14 00:03:57 UTC 2023
    - 34.6K bytes
    - Viewed (0)
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