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Results 51 - 60 of 159 for _conv (0.05 sec)
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src/cmd/internal/obj/arm/list5.go
package arm import ( "cmd/internal/obj" "fmt" ) func init() { obj.RegisterRegister(obj.RBaseARM, MAXREG, rconv) obj.RegisterOpcode(obj.ABaseARM, Anames) obj.RegisterRegisterList(obj.RegListARMLo, obj.RegListARMHi, rlconv) obj.RegisterOpSuffix("arm", obj.CConvARM) } func rconv(r int) string { if r == 0 { return "NONE" } if r == REGG { // Special case. return "g" }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jun 04 07:25:06 UTC 2020 - 3.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-tf-fake-quant-4bit.mlir
// CHECK: %[[DEQUANTIZE:.*]] = "tfl.dequantize"(%[[QUANTIZE]]) // CHECK: %[[CONV:.*]] = "tfl.conv_2d"(%arg0, %[[DEQUANTIZE]], %[[CONSTANT]]) // CHECK: return %[[CONV]] } // CHECK-LABEL: perChannelFakeQuantWithConv2D func.func @perChannelFakeQuantWithConv2D(tensor<256x32x32x3xf32>) -> (tensor<256x8x7x16xf32>) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 22K bytes - Viewed (0) -
src/cmd/internal/obj/mips/list0.go
// THE SOFTWARE. package mips import ( "cmd/internal/obj" "fmt" ) func init() { obj.RegisterRegister(obj.RBaseMIPS, REG_LAST+1, rconv) obj.RegisterOpcode(obj.ABaseMIPS, Anames) } func rconv(r int) string { if r == 0 { return "NONE" } if r == REGG { // Special case. return "g" } if REG_R0 <= r && r <= REG_R31 { return fmt.Sprintf("R%d", r-REG_R0)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 04 19:06:44 UTC 2020 - 2.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/add_dump_tensor_op.mlir
%1 = "tf.PartitionedCall"(%arg0, %cst, %cst_0) {_tfl_quant_trait = "fully_quantizable", config = "", config_proto = "", executor_type = "", f = @composite_conv2d_with_bias_and_relu6_fn_1} : (tensor<1x2x2x3xf32>, tensor<2x2x3x2xf32>, tensor<2xf32>) -> tensor<*xf32> loc(callsite("test@conv"("Conv2D_1") at "QuantizationUnit(\12\08Conv2D_1\1a\04conv)"))
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Mar 22 22:55:22 UTC 2024 - 37.9K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/list9.go
import ( "cmd/internal/obj" "fmt" ) func init() { obj.RegisterRegister(obj.RBasePPC64, REG_SPR0+1024, rconv) // Note, the last entry in Anames is "LASTAOUT", it is not a real opcode. obj.RegisterOpcode(obj.ABasePPC64, Anames[:len(Anames)-1]) obj.RegisterOpcode(AFIRSTGEN, GenAnames) } func rconv(r int) string { if r == 0 { return "NONE" } if r == REGG { // Special case. return "g" }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 15 21:12:43 UTC 2022 - 3.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-tf-fake-quant.mlir
// CHECK: %[[DEQUANTIZE:.*]] = "tfl.dequantize"(%[[QUANTIZE]]) // CHECK: %[[CONV:.*]] = "tfl.conv_2d"(%arg0, %[[DEQUANTIZE]], %[[CONSTANT]]) // CHECK: return %[[CONV]] } // CHECK-LABEL: perChannelFakeQuantWithConv2D func.func @perChannelFakeQuantWithConv2D(tensor<256x32x32x3xf32>) -> (tensor<256x8x7x16xf32>) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 20.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/dilated_conv.h
// dilation rate. // TF python library will rewrite dilated conv to // "SpaceToBatch->Conv->BatchToSpace" pattern, and the Conv in the middle // always has 'VALID' padding. The padding tensor in `SpaceToBatch` has two // parts of contributions, one is to reduce padding of CONV from 'SAME' to // 'VALID', and another is to make input shape multiples of dilation rate. The
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 20K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/stablehlo/tests/passes/insert_weight_param.mlir
return %0 : tensor<1x3x4x2xf32> } // CHECK: func private @composite_conv_fn // CHECK: %[[CONV:.+]] = stablehlo.convolution // CHECK: return %[[CONV]] } // ----- // Test that q/dq pair with per-channel quantization parameter is inserted // between constant and XlaCallModule op with `weight_only_ptq` method of
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 09 05:56:10 UTC 2024 - 22K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/default_quant_params.mlir
func.return %7 : tensor<1x112x112x32x!quant.uniform<u8:f32, 1.0>> // CHECK: %[[conv:.*]] = "tfl.conv_2d"(%arg0, %arg1, %arg2) // CHECK-SAME: -> tensor<1x112x112x32x!quant.uniform<u8:f32, 0.0078431372549019607:128>> // CHECK: %[[cst:.*]] = "tfl.pseudo_qconst"() // CHECK: %[[add:.*]] = tfl.add(%[[conv]], %[[cst]]) // CHECK-SAME: -> tensor<1x112x112x32x!quant.uniform<u8:f32, 1.000000e+00>> // CHECK: return %[[add]] }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 8.8K bytes - Viewed (0) -
src/cmd/compile/internal/walk/expr.go
if types.IsComplex[et] && n.Op() == ir.ODIV { t := n.Type() call := mkcall("complex128div", types.Types[types.TCOMPLEX128], init, typecheck.Conv(n.X, types.Types[types.TCOMPLEX128]), typecheck.Conv(n.Y, types.Types[types.TCOMPLEX128])) return typecheck.Conv(call, t) } // Nothing to do for float divisions. if types.IsFloat[et] { return n } // rewrite 64-bit div and mod on 32-bit architectures.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:34:01 UTC 2024 - 27.6K bytes - Viewed (0)