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Results 41 - 50 of 106 for umul (0.07 sec)

  1. src/cmd/asm/internal/asm/testdata/mips.s

    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADD	R1, R2
    
    	//	LADDW imm ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADD	$4, R1
    
    	//	LMUL rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MUL	R1, R2
    
    	//	LSHW rreg ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	SLL	R1, R2, R3
    
    	//	LSHW rreg ',' rreg
    	//	{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/arm/a.out.go

    	AFNMULAD
    	AFMULSF
    	AFMULSD
    	AFNMULSF
    	AFNMULSD
    	ADIVF
    	ADIVD
    	ASQRTF
    	ASQRTD
    	AABSF
    	AABSD
    	ANEGF
    	ANEGD
    
    	ASRL
    	ASRA
    	ASLL
    	AMULU
    	ADIVU
    	AMUL
    	AMMUL
    	ADIV
    	AMOD
    	AMODU
    	ADIVHW
    	ADIVUHW
    
    	AMOVB
    	AMOVBS
    	AMOVBU
    	AMOVH
    	AMOVHS
    	AMOVHU
    	AMOVW
    	AMOVM
    	ASWPBU
    	ASWPW
    
    	ARFE
    	ASWI
    	AMULA
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 05 16:22:12 UTC 2021
    - 7K bytes
    - Viewed (0)
  3. test/codegen/arithmetic.go

    	// 386:"SHLL\t[$]5",-"IMULL"
    	// arm:"SLL\t[$]5",-"MUL"
    	// arm64:"LSL\t[$]5",-"MUL"
    	// ppc64x:"SLD\t[$]5",-"MUL"
    	a := n1 * 32
    
    	// amd64:"SHLQ\t[$]6",-"IMULQ"
    	// 386:"SHLL\t[$]6",-"IMULL"
    	// arm:"SLL\t[$]6",-"MUL"
    	// arm64:`NEG\sR[0-9]+<<6,\sR[0-9]+`,-`LSL`,-`MUL`
    	// ppc64x:"SLD\t[$]6","NEG\\sR[0-9]+,\\sR[0-9]+",-"MUL"
    	b := -64 * n2
    
    	return a, b
    }
    
    func Mul_96(n int) int {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  4. src/cmd/vendor/golang.org/x/text/language/parse.go

    // in Accept-Language (with reasonable frequency).
    var acceptFallback = map[string]language.Language{
    	"english": _en,
    	"deutsch": _de,
    	"italian": _it,
    	"french":  _fr,
    	"*":       _mul, // defined in the spec to match all languages.
    }
    
    type tagSort struct {
    	tag []Tag
    	q   []float32
    }
    
    func (s *tagSort) Len() int {
    	return len(s.q)
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jan 24 13:01:26 UTC 2024
    - 7.5K bytes
    - Viewed (0)
  5. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

    		return true
    	case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC:
    		return true
    	case MODUD, MODSD, MODUW, MODSW:
    		return true
    	case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC:
    		return true
    	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
    		return true
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 10.9K bytes
    - Viewed (0)
  6. src/math/pow_s390x.s

    	SLD	$3, R0, R2
    	FMOVD	104(R9), F5
    	WORD	$0xED824004	//ldeb	%f8,4(%r2,%r4)
    	BYTE	$0x00
    	BYTE	$0x04
    	LDEBR	F3, F3
    	FMOVD	96(R9), F6
    	WFMADB	V4, V6, V5, V6
    	FADD	F8, F3
    	WFMADB	V7, V6, V16, V6
    	FMUL	F7, F7
    	FMOVD	88(R9), F5
    	FMADD	F7, F1, F6
    	WFMADB	V4, V5, V3, V16
    	FMOVD	80(R9), F1
    	WFSDB	V16, V3, V3
    	MOVD	$·powtl<>+0(SB), R3
    	WFMADB	V4, V6, V1, V6
    	FMADD	F5, F4, F3
    	FMOVD	72(R9), F1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jun 14 00:03:57 UTC 2023
    - 16.3K bytes
    - Viewed (0)
  7. src/math/atan2_s390x.s

    	VLEG	$0, 24(R9), V16
    	WFMADB	V1, V7, V18, V7
    	VLEG	$0, 16(R9), V18
    	VLEG	$0, 8(R9), V22
    	WFMADB	V4, V18, V16, V18
    	VLEG	$0, 0(R9), V16
    	WFMADB	V5, V6, V7, V6
    	WFMADB	V4, V16, V22, V16
    	FMUL	F3, F4
    	WFMADB	V1, V18, V16, V1
    	FMADD	F6, F5, F1
    	WFMADB	V4, V1, V3, V4
    	BLT	L18
    	BGT	L7
    	LTDBR	F2, F2
    	BLTU	L21
    L8:
    	LTDBR	F0, F0
    	BLTU	L22
    L9:
    	WFCHDBS	V2, V0, V0
    	BNE	L18
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 25 04:06:34 UTC 2020
    - 6.9K bytes
    - Viewed (0)
  8. src/cmd/vendor/golang.org/x/arch/x86/x86asm/plan9x.go

    	CVTTSD2SI: true,
    	CVTTSS2SI: true,
    	DEC:       true,
    	DIV:       true,
    	FLDENV:    true,
    	FRSTOR:    true,
    	IDIV:      true,
    	IMUL:      true,
    	IN:        true,
    	INC:       true,
    	LEA:       true,
    	MOV:       true,
    	MOVNTI:    true,
    	MUL:       true,
    	NEG:       true,
    	NOP:       true,
    	NOT:       true,
    	OR:        true,
    	OUT:       true,
    	POP:       true,
    	POPA:      true,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jul 12 20:38:21 UTC 2023
    - 7.2K bytes
    - Viewed (0)
  9. src/mdo/reader-stax.vm

            entities.put("Oslash", "\u00d8");
            entities.put("Ugrave", "\u00d9");
            entities.put("Uacute", "\u00da");
            entities.put("Ucirc", "\u00db");
            entities.put("Uuml", "\u00dc");
            entities.put("Yacute", "\u00dd");
            entities.put("THORN", "\u00de");
            entities.put("szlig", "\u00df");
            entities.put("agrave", "\u00e0");
            entities.put("aacute", "\u00e1");
    Registered: Wed Jun 12 09:55:16 UTC 2024
    - Last Modified: Mon Mar 25 10:50:01 UTC 2024
    - 38.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    (Sub(32|64)F ...) => (SUBS(S|D) ...)
    
    (Mul(64|32|16|8) ...) => (MUL(Q|L|L|L) ...)
    (Mul(32|64)F ...) => (MULS(S|D) ...)
    
    (Select0 (Mul64uover x y)) => (Select0 <typ.UInt64> (MULQU x y))
    (Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y))
    (Select1 (Mul(64|32)uover x y)) => (SETO (Select1 <types.TypeFlags> (MUL(Q|L)U x y)))
    
    (Hmul(64|32) ...) => (HMUL(Q|L) ...)
    (Hmul(64|32)u ...) => (HMUL(Q|L)U ...)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
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