MOVD	$-1, acc0
	MOVD	p256const0<>(SB), acc1
	MOVD	$0, acc2
	MOVD	p256const1<>(SB), acc3
	// Load the original value
	LDP	0*16(a_ptr), (t0, t1)
	LDP	1*16(a_ptr), (t2, t3)
	// Speculatively subtract
	SUBS	t0, acc0
	SBCS	t1, acc1
	SBCS	t2, acc2
	SBC	t3, acc3
	// If condition is 0, keep original value
	CMP	$0, hlp0
	CSEL	EQ, t0, acc0, acc0
	CSEL	EQ, t1, acc1, acc1
	CSEL	EQ, t2, acc2, acc2

					if q, ok := s.(*Qualified); ok {
						a := q.Scope
						if t, ok := a.(*Template); ok {
							st.subs.add(t.Name)
							st.subs.add(t)
						} else {
							st.subs.add(a)
						}
						return s
					}
				}
				n := st.sourceName()
				if len(st.str) > 0 && st.str[0] == 'I' {
					st.subs.add(n)
					args := st.templateArgs()
					n = &Template{Name: n, Args: args}
				}

	VLD1.P	64(R2), [V4.B16, V5.B16, V6.B16, V7.B16]
	VEOR	V0.B16, V4.B16, V4.B16
	VEOR	V1.B16, V5.B16, V5.B16
	VEOR	V2.B16, V6.B16, V6.B16
	VEOR	V3.B16, V7.B16, V7.B16
	VST1.P	[V4.B16, V5.B16, V6.B16, V7.B16], 64(R0)
	SUBS	$64, R3
	CMP	$64, R3
	BGE	loop_64
tail:
	// quick end
	CBZ	R3, end
	TBZ	$5, R3, less_than32
	VLD1.P	32(R1), [V0.B16, V1.B16]
	VLD1.P	32(R2), [V2.B16, V3.B16]
	VEOR	V0.B16, V2.B16, V2.B16

	AFRINTIS
	AFRINTMD
	AFRINTMS
	AFRINTND
	AFRINTNS
	AFRINTPD
	AFRINTPS
	AFRINTXD
	AFRINTXS
	AFRINTZD
	AFRINTZS
	AFSQRTD
	AFSQRTS
	AFSTPD
	AFSTPQ
	AFSTPS
	AFSUBD
	AFSUBS
	AHINT
	AHLT
	AHVC
	AIC
	AISB
	ALDADDAB
	ALDADDAD
	ALDADDAH
	ALDADDALB
	ALDADDALD
	ALDADDALH
	ALDADDALW
	ALDADDAW
	ALDADDB
	ALDADDD
	ALDADDH
	ALDADDLB

	for i > 0 && p.stack[i-1].Op < opPseudo {
		i--
	}
	subs := p.stack[i:]
	p.stack = p.stack[:i]

	// Make sure top class is clean.
	// All the others already are (see swapVerticalBar).
	if len(subs) > 0 {
		cleanAlt(subs[len(subs)-1])
	}

	// Empty alternate is special case
	// (shouldn't happen but easy to handle).
	if len(subs) == 0 {
		return p.push(p.newRegexp(OpNoMatch))
	}

	SUBS	$0xff, R6, RSP                                   // ERROR "illegal destination register"
	SUBS	$0xffff0, R6, RSP                                // ERROR "illegal destination register"
	SUBS	$0x1000100010001000, R6, RSP                     // ERROR "illegal destination register"
	SUBS	$0x10001000100011, R6, RSP                       // ERROR "illegal destination register"

The anatomy of a typical project root directory looks as follows:

[listing,subs=+macros]
----
├── .gradle                 // <1>
│   ├── 4.8                     // <2>
│   ├── 4.9                     // <2>
│   └── ⋮
├── build                   // <3>
├── gradle

dependencies {
    conf 'foo:bar:1'
    conf project(':sub')
}

configurations.all {
  resolutionStrategy {
      dependencySubstitution { DependencySubstitutions subs ->
          subs.substitute(subs.module('foo:bar:1')).using(subs.project(':sub'))
      }
      failOnVersionConflict()
  }
}

"""

        when:
        succeeds ':checkDeps'

        then:

	FSCALE:          "FSCALE",
	FSIN:            "FSIN",
	FSINCOS:         "FSINCOS",
	FSQRT:           "FSQRT",
	FST:             "FST",
	FSTP:            "FSTP",
	FSUB:            "FSUB",
	FSUBP:           "FSUBP",
	FSUBR:           "FSUBR",
	FSUBRP:          "FSUBRP",
	FTST:            "FTST",
	FUCOM:           "FUCOM",
	FUCOMI:          "FUCOMI",
	FUCOMIP:         "FUCOMIP",
	FUCOMP:          "FUCOMP",

	OpRepeat                       // matches Sub[0] at least Min times, at most Max (Max == -1 is no limit)
	OpConcat                       // matches concatenation of Subs
	OpAlternate                    // matches alternation of Subs
)

const opPseudo Op = 128 // where pseudo-ops start

// Equal reports whether x and y have identical structure.
func (x *Regexp) Equal(y *Regexp) bool {
	if x == nil || y == nil {