{name: "SRAW", argLength: 2, reg: sh21, asm: "SRAW", clobberFlags: true},                    // signed int32(arg0) >> arg1, shift amount is mod 64
		{name: "SRADconst", argLength: 1, reg: gp11, asm: "SRAD", aux: "UInt8", clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-63

correct result, and the assembler does not add extra checking.

Examples:

	SRAD $8,R3,R4		=>	sradi r4,r3,8
	SRD $8,R3,R4		=>	rldicl r4,r3,56,8
	SLD $8,R3,R4		=>	rldicr r4,r3,8,55
	SRAW $16,R4,R5		=>	srawi r5,r4,16
	SRW $40,R4,R5		=>	rlwinm r5,r4,0,0,31
	SLW $12,R4,R5		=>	rlwinm r5,r4,12,0,19

Some non-simple shifts have operands in the Go assembly which don't map directly

	VPSLLW $-1, X1, X2           // c5e971f1ff
	VPSLLW $-1, Y1, Y2           // c5ed71f1ff
	VPSRAD $-1, X1, X2           // c5e972e1ff
	VPSRAD $-1, Y1, Y2           // c5ed72e1ff
	VPSRAW $-1, X1, X2           // c5e971e1ff
	VPSRAW $-1, Y1, Y2           // c5ed71e1ff
	VPSRLW $-1, X1, X1           // c5f171d1ff
	VPSRLW $-1, Y1, Y2           // c5ed71d1ff
	VEXTRACTPS $-1, X1, AX       // c4e37917c8ff

		v.AuxInt = int64ToAuxInt(int64(y) >> uint32(x))
		return true
	}
	return false
}
func rewriteValueRISCV64_OpRISCV64SRAW(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SRAW x (MOVDconst [val]))
	// result: (SRAIW [int64(val&31)] x)
	for {
		x := v_0
		if v_1.Op != OpRISCV64MOVDconst {
			break
		}
		val := auxIntToInt64(v_1.AuxInt)
		v.reset(OpRISCV64SRAIW)

	/*4771*/ uint16(xMatch),
	/*4772*/ uint16(xCondPrefix), 2,
	0x66, 4784,
	0x0, 4778,
	/*4778*/ uint16(xSetOp), uint16(PSRAW),
	/*4780*/ uint16(xReadIb),
	/*4781*/ uint16(xArgMm2),
	/*4782*/ uint16(xArgImm8u),
	/*4783*/ uint16(xMatch),
	/*4784*/ uint16(xSetOp), uint16(PSRAW),
	/*4786*/ uint16(xReadIb),
	/*4787*/ uint16(xArgXmm2),
	/*4788*/ uint16(xArgImm8u),
	/*4789*/ uint16(xMatch),

	// Expand binary instructions to ternary ones.
	if p.Reg == obj.REG_NONE {
		switch p.As {
		case AADDI, ASLTI, ASLTIU, AANDI, AORI, AXORI, ASLLI, ASRLI, ASRAI,
			AADDIW, ASLLIW, ASRLIW, ASRAIW, AADDW, ASUBW, ASLLW, ASRLW, ASRAW,
			AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA,
			AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW,
			AREM, AREMU, AREMW, AREMUW,
			AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,

	VADDUBM  XC2, XC2, XC2       // 0xc2...
	VSPLTISB $7, T2
	VOR      XC2, T1, XC2        // 0xc2....01
	VSPLTB   $0, H, T1           // most significant byte
	VSL      H, T0, H            // H<<=1
	VSRAB    T1, T2, T1          // broadcast carry bit
	VAND     T1, XC2, T1
	VXOR     H, T1, IN           // twisted H

	VSLDOI $8, IN, IN, H      // twist even more ...
	VSLDOI $8, ZERO, XC2, XC2 // 0xc2.0

	"XSCMPGTQP",
	"XSCMPGEQP",
	"XSCMPEQQP",
	"VSTRIHRCC",
	"VSTRIHR",
	"VSTRIHLCC",
	"VSTRIHL",
	"VSTRIBRCC",
	"VSTRIBR",
	"VSTRIBLCC",
	"VSTRIBL",
	"VSRQ",
	"VSRDBI",
	"VSRAQ",
	"VSLQ",
	"VSLDBI",
	"VRLQNM",
	"VRLQMI",
	"VRLQ",
	"VPEXTD",
	"VPDEPD",
	"VMULOUD",
	"VMULOSD",
	"VMULLD",
	"VMULHUW",
	"VMULHUD",
	"VMULHSW",
	"VMULHSD",
	"VMULEUD",

	// match: (Rsh32x16 x y)
	// cond: shiftIsBounded(v)
	// result: (SRAW x y)
	for {
		x := v_0
		y := v_1
		if !(shiftIsBounded(v)) {
			break
		}
		v.reset(OpPPC64SRAW)
		v.AddArg2(x, y)
		return true
	}
	// match: (Rsh32x16 <t> x y)
	// result: (ISEL [2] (SRAW <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0xFFE0] y)))
	for {
		t := v.Type

			opset(AOR, r)
			opset(AXOR, r)
		case AANDW:
			opset(AORW, r)
			opset(AXORW, r)
		case ASLD:
			opset(ASRD, r)
			opset(ASLW, r)
			opset(ASRW, r)
			opset(ASRAD, r)
			opset(ASRAW, r)
			opset(ARLL, r)
			opset(ARLLG, r)
		case ARNSBG:
			opset(ARXSBG, r)
			opset(AROSBG, r)
			opset(ARNSBGT, r)
			opset(ARXSBGT, r)
			opset(AROSBGT, r)
			opset(ARISBG, r)