github.com/goccy/go-json v0.10.2 // indirect
	github.com/google/uuid v1.6.0 // indirect
	github.com/klauspost/compress v1.17.8 // indirect
	github.com/klauspost/cpuid/v2 v2.2.7 // indirect
	github.com/minio/md5-simd v1.1.2 // indirect
	github.com/rs/xid v1.5.0 // indirect
	github.com/stretchr/testify v1.7.0 // indirect
	golang.org/x/crypto v0.23.0 // indirect
	golang.org/x/net v0.25.0 // indirect
	golang.org/x/sys v0.20.0 // indirect

		Comment("Iteration " + strconv.Itoa(i))
		hi, lo := RDX, RAX // implicit MULQ inputs and outputs
		MOVQ(x.Offset(i*8), lo)
		MULQ(y)
		ADDQ(z.Offset(i*8), lo)
		ADCQ(Imm(0), hi)
		ADDQ(carry, lo)
		ADCQ(Imm(0), hi)
		MOVQ(hi, carry)
		MOVQ(lo, z.Offset(i*8))
	}

	Store(carry, ReturnIndex(0))
	RET()

	Label("adx")

	// The ADX strategy implements the following function, where c1 and c2 are

			}
		}
	}
}

// An Imm is an integer constant.
type Imm struct {
	Imm     uint32
	Decimal bool
}

func (Imm) isArg() {}

func (i Imm) String() string {
	if !i.Decimal {
		return fmt.Sprintf("#%#x", i.Imm)
	} else {
		return fmt.Sprintf("#%d", i.Imm)
	}
}

type Imm64 struct {
	Imm     uint64
	Decimal bool
}

func (Imm64) isArg() {}

		dst.Ints[i] = uintptr(src.regs[i])
	}
	for i := range dst.Floats {
		dst.Floats[i] = *(fpRegAddr(src, i))
	}
}

// fpRegAddr returns the address of the ith fp-simd register in sigcontext.
func fpRegAddr(dst *sigcontext, i int) *uint64 {
	/* FP-SIMD registers are saved in sigcontext.__reserved, which is orgnized in
	the following C structs:
	struct fpsimd_context {
		struct _aarch64_ctx head;
		__u32 fpsr;
		__u32 fpcr;

      <w>externref</w>
      <w>funcref</w>
      <w>jetbrains</w>
      <w>kotlinx</w>
      <w>ktor</w>
      <w>optref</w>
      <w>popcnt</w>
      <w>rotl</w>
      <w>rotr</w>
      <w>simd</w>
      <w>sqrt</w>
      <w>testsuite</w>
      <w>uninstantiable</w>
      <w>unintercepted</w>
      <w>unlinkable</w>
      <w>vtable</w>
      <w>wabt</w>
      <w>xopt</w>
    </words>

      FormBody.Builder()
        .add("sim", "ple")
        .build()
    val expected = "sim=ple"
    assertThat(body.contentLength()).isEqualTo(expected.length.toLong())
    val buffer = Buffer()
    body.writeTo(buffer)
    assertThat(buffer.readUtf8()).isEqualTo(expected)
  }

  @Test
  fun encodeMultiplePairs() {
    val body =
      FormBody.Builder()
        .add("sim", "ple")
        .add("hey", "there")

type facility uint8

const (
	// mandatory facilities
	zarch  facility = 1  // z architecture mode is active
	stflef facility = 7  // store-facility-list-extended
	ldisp  facility = 18 // long-displacement
	eimm   facility = 21 // extended-immediate

	// miscellaneous facilities
	dfp    facility = 42 // decimal-floating-point
	etf3eh facility = 30 // extended-translation 3 enhancement

	// cryptography facilities

	options = []option{
		{Name: "zarch", Feature: &S390X.HasZARCH, Required: true},
		{Name: "stfle", Feature: &S390X.HasSTFLE, Required: true},
		{Name: "ldisp", Feature: &S390X.HasLDISP, Required: true},
		{Name: "eimm", Feature: &S390X.HasEIMM, Required: true},
		{Name: "dfp", Feature: &S390X.HasDFP},
		{Name: "etf3eh", Feature: &S390X.HasETF3EH},
		{Name: "msa", Feature: &S390X.HasMSA},
		{Name: "aes", Feature: &S390X.HasAES},

		}
		return op + " (" + args[1] + ")(" + args[0] + ")"

	// branch instructions needs additional handling
	case BCLR:
		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
			return "RET"
		}
		return op + " " + strings.Join(args, ", ")
	case BC:
		bo := int(inst.Args[0].(Imm))
		bi := int(inst.Args[1].(CondReg) - Cond0LT)
		bcname := condName[((bo&0x8)>>1)|(bi&0x3)]

		var err error
		var imm, immMask int64
		switch r.Type() {
		case objabi.R_RISCV_RVC_BRANCH:
			immMask = riscv.CBTypeImmMask
			imm, err = riscv.EncodeCBImmediate(off)
			if err != nil {
				ldr.Errorf(s, "cannot encode CB-type instruction relocation offset for %s: %v", ldr.SymName(rs), err)
			}
		case objabi.R_RISCV_RVC_JUMP:
			immMask = riscv.CJTypeImmMask
			imm, err = riscv.EncodeCJImmediate(off)