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Results 21 - 30 of 111 for div0 (0.05 sec)

  1. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/x86/anames.go

    	"CVTTSD2SL",
    	"CVTTSD2SQ",
    	"CVTTSS2SL",
    	"CVTTSS2SQ",
    	"CWD",
    	"CWDE",
    	"DAA",
    	"DAS",
    	"DECB",
    	"DECL",
    	"DECQ",
    	"DECW",
    	"DIVB",
    	"DIVL",
    	"DIVPD",
    	"DIVPS",
    	"DIVQ",
    	"DIVSD",
    	"DIVSS",
    	"DIVW",
    	"DPPD",
    	"DPPS",
    	"EMMS",
    	"ENTER",
    	"EXTRACTPS",
    	"F2XM1",
    	"FABS",
    	"FADDD",
    	"FADDDP",
    	"FADDF",
    	"FADDL",
    	"FADDW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
  4. src/math/big/natconv.go

    //
    // The iterative method processes n Words by n divW() calls, each of which visits every Word in the
    // incrementally shortened q for a total of n + (n-1) + (n-2) ... + 2 + 1, or n(n+1)/2 divW()'s.
    // Recursive conversion divides q by its approximate square root, yielding two parts, each half
    // the size of q. Using the iterative method on both halves means 2 * (n/2)(n/2 + 1)/2 divW()'s
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Nov 18 17:59:44 UTC 2022
    - 14.6K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/ir/tf_traits.h

        return a;
      }
      int64_t rank = a.getRank();
      SmallVector<int64_t, 4> dims;
      dims.resize(rank);
      for (int i = 0, e = rank; i != e; i++) {
        int64_t dim0 = a.getDimSize(i);
        int64_t dim1 = b.getDimSize(i);
        dims[i] = (dim0 == ShapedType::kDynamic) ? dim1 : dim0;
      }
      return RankedTensorType::get(dims, a.getElementType());
    }
    }  // namespace detail
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  6. src/runtime/time_windows_386.s

    	// nano/100 = DX:AX
    	// split into two decimal halves by div 1e9.
    	// (decimal point is two spots over from correct place,
    	// but we avoid overflow in the high word.)
    	MOVL	$1000000000, CX
    	DIVL	CX
    	MOVL	AX, DI
    	MOVL	DX, SI
    
    	// DI = nano/100/1e9 = nano/1e11 = sec/100, DX = SI = nano/100%1e9
    	// split DX into seconds and nanoseconds by div 1e7 magic multiply.
    	MOVL	DX, AX
    	MOVL	$1801439851, CX
    	MULL	CX
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Sep 07 17:19:45 UTC 2023
    - 1.7K bytes
    - Viewed (0)
  7. src/runtime/vlop_386.s

    	ADDL	AX, BX
    	ADCL	$0, DX
    	MOVL	BX, 4(CX)
    	MOVL	DX, AX
    	MOVL	AX, hi32+16(FP)
    	RET
    
    TEXT runtimeĀ·_div64by32(SB), NOSPLIT, $0
    	MOVL	r+12(FP), CX
    	MOVL	a_lo+0(FP), AX
    	MOVL	a_hi+4(FP), DX
    	DIVL	b+8(FP)
    	MOVL	DX, 0(CX)
    	MOVL	AX, q+16(FP)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jun 04 07:25:06 UTC 2020
    - 2K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/lite/stablehlo/transforms/legalize_hlo_patterns.td

                  (MHLO_AddOp
                    (MHLO_DivOp:$div
                      (MHLO_SubtractOp $arg0, $rem2),
                      $arg1b),
                    (MHLO_ConstantOp $cst_neg1)),
                  $div1)),
              (TF_FloorDivOp $arg0, $arg1),
              [(ValueEquals<"0.0"> $cst),
               (ValueEquals<"-1.0"> $cst_neg1),
               (SameValue $div, $div1),
               (SameValue $rem, $rem1),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Feb 03 08:58:22 UTC 2024
    - 34K bytes
    - Viewed (0)
  9. pkg/kubelet/apis/podresources/server_v1alpha1_test.go

    	podNamespace := "pod-namespace"
    	podUID := types.UID("pod-uid")
    	containerName := "container-name"
    
    	devs := []*podresourcesv1.ContainerDevices{
    		{
    			ResourceName: "resource",
    			DeviceIds:    []string{"dev0", "dev1"},
    		},
    	}
    
    	mockCtrl := gomock.NewController(t)
    	defer mockCtrl.Finish()
    
    	for _, tc := range []struct {
    		desc             string
    		pods             []*v1.Pod
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Thu Mar 07 08:12:16 UTC 2024
    - 3.9K bytes
    - Viewed (0)
  10. src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go

    	{VNMLA_EQ_F64, []int{2, 1, 0}, "VNMLA", "NMULAD"},
    	{VNMLS_EQ_F32, []int{2, 1, 0}, "VNMLS", "NMULSF"},
    	{VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"},
    	{VDIV_EQ_F32, []int{2, 1, 0}, "VDIV", "DIVF"},
    	{VDIV_EQ_F64, []int{2, 1, 0}, "VDIV", "DIVD"},
    	{VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"},
    	{VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"},
    	{VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"},
    	{VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 11.9K bytes
    - Viewed (0)
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