var S390Xops = []opData{
		// fp ops
		{name: "FADDS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FADDS", commutative: true, resultInArg0: true}, // fp32 arg0 + arg1
		{name: "FADD", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FADD", commutative: true, resultInArg0: true},   // fp64 arg0 + arg1

	DPPD:            "DPPD",
	DPPS:            "DPPS",
	EMMS:            "EMMS",
	ENTER:           "ENTER",
	EXTRACTPS:       "EXTRACTPS",
	F2XM1:           "F2XM1",
	FABS:            "FABS",
	FADD:            "FADD",
	FADDP:           "FADDP",
	FBLD:            "FBLD",
	FBSTP:           "FBSTP",
	FCHS:            "FCHS",
	FCMOVB:          "FCMOVB",
	FCMOVBE:         "FCMOVBE",
	FCMOVE:          "FCMOVE",

	DCBZ:           "dcbz",
	EQV:            "eqv",
	EQVCC:          "eqv.",
	EXTSH:          "extsh",
	EXTSHCC:        "extsh.",
	FABS:           "fabs",
	FABSCC:         "fabs.",
	FADD:           "fadd",
	FADDCC:         "fadd.",
	FCMPO:          "fcmpo",
	FCMPU:          "fcmpu",
	FDIV:           "fdiv",
	FDIVCC:         "fdiv.",
	FMADD:          "fmadd",
	FMADDCC:        "fmadd.",

// license that can be found in the LICENSE file.

// Lowering arithmetic
(Add(64|Ptr) ...) => (ADD ...)
(Add(32|16|8) ...) => (ADDW ...)
(Add32F x y) => (Select0 (FADDS x y))
(Add64F x y) => (Select0 (FADD x y))

(Sub(64|Ptr) ...) => (SUB ...)
(Sub(32|16|8) ...) => (SUBW ...)
(Sub32F x y) => (Select0 (FSUBS x y))
(Sub64F x y) => (Select0 (FSUB x y))

(Mul64 ...) => (MULLD ...)
(Mul(32|16|8) ...) => (MULLW ...)

{"Name":"FADD (vector)","Bits":"0|Q|0|0|1|1|1|0|0|sz|1|Rm:5|1|1|0|1|0|1|Rn:5|Rd:5","Arch":"Vector single-precision and double-precision variant","Syntax":"FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>","Code":"","Alias":""},
{"Name":"FADD (scalar)","Bits":"0|0|0|1|1|1|1|0|00:2|1|Rm:5|0|0|1|0|1|0|Rn:5|Rd:5","Arch":"Single-precision variant","Syntax":"FADD <Sd>, <Sn>, <Sm>","Code":"","Alias":""},

		o1 = OP_RRR(a, p.From.Reg, obj.REG_NONE, p.To.Reg)

	case 31: /* movw fr,r */
		a := SP(2, 1) | (0 << 21) /* mtc1 */
		o1 = OP_RRR(a, p.To.Reg, obj.REG_NONE, p.From.Reg)

	case 32: /* fadd fr1,[fr2],fr3 */
		r := p.Reg
		if r == obj.REG_NONE {
			r = p.To.Reg
		}
		o1 = OP_FRRR(c.oprrr(p.As), p.From.Reg, r, p.To.Reg)

	case 33: /* fabs fr1, fr3 */

				// assembler source (that is, what is left on each line of the
				// compile -S output after we strip file/line info) to avoid
				// trivial bugs such as "ADD" matching "FADD". This
				// doesn't remove genericity: it's still possible to write
				// something like "F?ADD", but we make common cases simpler
				// to get right.
				oprx, err := regexp.Compile("^" + rxsrc)

// GOPPC64 values indicate power8, power9, etc.
// That means the code is compiled for that target,
// and will not run on earlier targets.
//
(Add(Ptr|64|32|16|8) ...) => (ADD ...)
(Add64F ...) => (FADD ...)
(Add32F ...) => (FADDS ...)

(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
(Sub32F ...) => (FSUBS ...)
(Sub64F ...) => (FSUB ...)

(Min(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMINJDP x y)

		o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))

	case 31: // movw fr,r
		a := OP_TEN(8, 1325) // movfr2gr.s
		o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))

	case 32: // fadd fr1,[fr2],fr3
		r := int(p.Reg)
		if r == 0 {
			r = int(p.To.Reg)
		}
		o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))

	case 33: // fabs fr1, fr3

		return true
	}
}
func rewriteValueS390X_OpAdd64F(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Add64F x y)
	// result: (Select0 (FADD x y))
	for {
		x := v_0
		y := v_1
		v.reset(OpSelect0)
		v0 := b.NewValue0(v.Pos, OpS390XFADD, types.NewTuple(typ.Float64, types.TypeFlags))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}