BC $16,CR0LT,0(PC)              // 42000000
	BCL $16,CR0LT,0(PC)             // 42000001
	BC $18,CR0LT,0(PC)              // 42400000

	MOVD SPR(3), 4(R1)              // 7fe302a6fbe10004
	MOVD XER, 4(R1)                 // 7fe102a6fbe10004
	MOVD 4(R1), SPR(3)              // ebe100047fe303a6
	MOVD 4(R1), XER                 // ebe100047fe103a6
	OR $0, R0, R0                   // 60000000

		if p.To.Reg == 0 {
			c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
		}
		o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12

	case 66: /* mov spr,r1; mov r1,spr */
		var r int
		var v int32
		if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
			r = int(p.From.Reg)
			v = int32(p.To.Reg)
			o1 = OPVCC(31, 467, 0, 0) /* mtspr */
		} else {

	// ARM64 only.
	if p.arch.Family != sys.ARM64 {
		return false
	}
	// R1.xxx
	return p.peek() == '.'
}

// registerReference parses a register given either the name, R10, or a parenthesized form, SPR(10).
func (p *Parser) registerReference(name string) (int16, bool) {
	r, present := p.arch.Register[name]
	if present {
		return r, true
	}
	if !p.arch.RegisterPrefix[name] {

	MOVD	R4, LR
	RET

TEXT runtime·abort(SB),NOSPLIT|NOFRAME,$0-0
	MOVW	(R0), R0
	UNDEF

#define	TBR	268

// int64 runtime·cputicks(void)
TEXT runtime·cputicks(SB),NOSPLIT,$0-8
	MOVD	SPR(TBR), R3
	MOVD	R3, ret+0(FP)
	RET

// spillArgs stores return values from registers to a *internal/abi.RegArgs in R20.
TEXT runtime·spillArgs(SB),NOSPLIT,$0-0
	MOVD    R3, 0(R20)
	MOVD    R4, 8(R20)

		rt, r, rf := p.To.Reg, p.From.Reg, int16(REGTMP)
		if r == obj.REG_NONE {
			r = o.param
		}
		o2 = c.opxrrr(p, AADD, rt, r, rf, false)
		o2 |= LSL0_64

	case 35: /* mov SPR,R -> mrs */
		o1 = c.oprrr(p, AMRS)

		// SysRegEnc function returns the system register encoding and accessFlags.
		_, v, accessFlags := SysRegEnc(p.From.Reg)
		if v == 0 {

		[6]*argField{ap_Reg_6_10}},
	{MFSPR, 0xfc0007fe00000000, 0x7c0002a600000000, 0x100000000, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
		[6]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
	{MTCRF, 0xfc1007fe00000000, 0x7c00012000000000, 0x80100000000, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS)
		[6]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},