```

### 2. Create a sample OPA Policy

In another terminal, create a policy that allows root user all access and for all other users denies `PutObject`:

```sh
cat > example.rego <<EOF
package httpapi.authz

import input

default allow = false

# Allow the root user to perform any action.
allow {
 input.owner == true
}

Joe Tsai <******@****.***> 1443691829 -0700

        // Count how many registrations this affects
        int affectedRegistrations = 0;
        for (MockRegistration reg : registrations.values()) {
            if (reg.shareName.equalsIgnoreCase(resourceName) || reg.serverAddress.equals(resourceName)) {
                affectedRegistrations++;
            }
        }

			// the CR bit.
			prog.Reg = a[1].Reg
			if a[1].Type != obj.TYPE_REG {
				// The CR bit is represented as a constant 0-31. Convert it to a Reg.
				c := p.getConstant(prog, op, &a[1])
				reg, success := ppc64.ConstantToCRbit(c)
				if !success {
					p.errorf("invalid CR bit register number %d", c)
				}
				prog.Reg = reg
			}
			break
		}

        WitnessRegisterResponse mockResponse = mock(WitnessRegisterResponse.class);
        lenient().when(mockResponse.isSuccess()).thenReturn(true);
        lenient().when(mockResponse.getRegistrationId()).thenReturn("test-reg-123");

        WitnessRpcClient mockRpc = mock(WitnessRpcClient.class);
        lenient().when(mockRpc.register(any(WitnessRegisterRequest.class))).thenReturn(mockResponse);

}

// ARM64RegisterShift constructs an ARM64 register with shift operation.
func ARM64RegisterShift(reg, op, count int16) (int64, error) {
	// the base register of shift operations must be general register.
	if reg > arm64.REG_R31 || reg < arm64.REG_R0 {
		return 0, errors.New("invalid register for shift operation")
	}
	return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
}

			"\tb\\",
			"\tc",
			"before",
			"A(1, 2, 3)",
			"after",
		),
		"before.\n.1.\n.2.\n.3.\n.after.\n",
	},
	{
		"LOAD macro",
		lines(
			"#define LOAD(off, reg) \\",
			"\tMOVBLZX	(off*4)(R12),	reg \\",
			"\tADDB	reg,		DX",
			"",
			"LOAD(8, AX)",
		),
		"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n",
	},
	{
		"nested multiline macro",
		lines(

		return true
	}
	return false
}

// IsARMBFX reports whether the op (as defined by an arm.A* constant) is one the
// BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg".
func IsARMBFX(op obj.As) bool {
	switch op {
	case arm.ABFX, arm.ABFXU, arm.ABFC, arm.ABFI:
		return true
	}
	return false
}

WAY","Route":"01521","Agency":1,"ViolationCode":"4000A1","ViolationDescr":"NO EVIDENCE OF REG","Fine":50,"Latitude":99999,"Longitude":99999} {"Ticket":1103700150,"IssueData":"2015-12-21T00:00:00","IssueTime":"1435","RPState":"CA","PlateExpiry":"201512","Make":"GMC","BodyStyle":"VN","Color":"WH","Location":"525 S MAIN ST","Route":"1C51","Agency":1,"ViolationCode":"4000A1","ViolationDescr":"NO EVIDENCE OF REG","Fine":50,"Latitude":99999,"Longitude":99999} {"Ticket":1104803000,"IssueData":"2015-12-...

// MULL r1,r2,(hi,lo)
//
//	LTYPEM cond reg ',' reg ',' regreg
//	{
//		outcode($1, $2, &$3, int32($5.Reg), &$7);
//	}
	MULL	R1, R2, (R3,R4)

//
// MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4
// MULAW{T,B} r1,r2,r3,r4
//
//	LTYPEN cond reg ',' reg ',' reg ',' spreg
//	{
//		$7.Type = obj.TYPE_REGREG2;
//		$7.Offset = int64($9);
//		outcode($1, $2, &$3, int32($5.Reg), &$7);
//	}
	MULAWT	R1, R2, R3, R4