// Prefetch instruction
		// Do prefetch of address generated with arg0 and arg1 with option aux. arg0=addr,arg1=memory, aux=option.
		{name: "DCBT", argLength: 2, aux: "Int64", reg: prefreg, asm: "DCBT", hasSideEffects: true},

		// Store bytes in the reverse endian order of the arch into arg0.
		// These are indexed stores with no offset field in the instruction so the auxint fields are not used.

BD,IAAgB,MAAhBA,EAE9BkD,EAAS,KACRnD,EAAY+C,EAAe3C,GAA3BJ,CAAiC+C,EAAeJ,SADxC,MAEPzC,EAAa6C,EAAezC,IAA5BJ,CAAmC6C,EAAeH,UAF3C,QAAA,SAAA,QAORZ,MCTT,aAAyC,IACjChF,GAAWR,EAAQQ,YACR,MAAbA,MAAoC,MAAbA,iBAG2B,OAAlDK,OAAkC,UAAlCA,cAGEJ,GAAaU,KARoB,WAYhCyF,KCbT,aAA8D,IAEvD,IAAY,CAAC5G,EAAQ6G,aAArB,EAAsCnF,UAClCf,UAASa,gBAH0C,OAKxDsF,GAAK9G,EAAQ6G,aAL2C,CAMrDC,GAAoD,MAA9CjG,OAA6B,WAA7BA,CAN+C,IAOrDiG,EAAGD,oBAEHC,IAAMnG,SAASa,gBCExB,mBAME,IADAiE,4CAAAA,eAIIsB,EAAa,CAAEnD,IAAK,CAAP,CAAUE,KAAM,CAAhB,EACXnC,...

hyatt

// hyundai : 2015-07-09 Hyundai Motor Company
hyundai

// ibm : 2014-07-31 International Business Machines Corporation
ibm

// icbc : 2015-02-19 Industrial and Commercial Bank of China Limited
icbc

// ice : 2014-10-30 IntercontinentalExchange, Inc.
ice

// icu : 2015-01-08 ShortDot SA
icu

// ieee : 2015-07-23 IEEE Global LLC
ieee

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e???s&citsigol?e&civres?r??krow?serp!xe??tnega??t&farcr&ia?otor??hgil&f?orcim??liubemoh?n&atlusnoc?e&duts?m&esuma?n&iatretne?revog??piuqe????olip?ropria?si&lanruoj?tneics???w&erc?ohs??y&cnegreme?dobper?tefas????rref?z??p!.&a&aa?ca?pc??dem?ecartsnd.icb,gne?korgn,r&ab?uj??s&nduolc,rahc21,?t&acova?cca?hcer??wal?ysrab,???s!.&em?gro?hcs,moc?syevrus,ten?ude?vog???t!.&0x,116,ayo,gro?lim?moc?nayn,sulpnpv,t&cennockciuq.tcerid,en??ude?v&dr,og???o&hp?m?v?yk??tol?ua??v&iv?lov??xas?ykot??p&a&ehc?g?m?s??eej?g...

hápmir.no häkkinen.fi hå.no hægebostad.no hønefoss.no høyanger.no høylandet.no i.bg i.ng i.ph i.se i234.me ia.us iamallama.com ibara.okayama.jp ibaraki.ibaraki.jp ibaraki.jp ibaraki.osaka.jp ibestad.no ibigawa.gifu.jp ibm ibxos.it ic.gov.pl icbc ice ichiba.tokushima.jp ichihara.chiba.jp ichikai.tochigi.jp ichikawa.chiba.jp ichikawa.hyogo.jp ichikawamisato.yamanashi.jp ichinohe.iwate.jp ichinomiya.aichi.jp ichinomiya.chiba.jp ichinoseki.iwate.jp icu icurus.jp id id.au id.firewalledreplit.co...

		}
		o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11

	case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */
		/* TH field for dcbt/dcbtst: */
		/* 0 = Block access - program will soon access EA. */
		/* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */

		v.AddArg(v0)
		return true
	}
}
func rewriteValuePPC64_OpPrefetchCache(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (PrefetchCache ptr mem)
	// result: (DCBT ptr mem [0])
	for {
		ptr := v_0
		mem := v_1
		v.reset(OpPPC64DCBT)
		v.AuxInt = int64ToAuxInt(0)
		v.AddArg2(ptr, mem)
		return true
	}
}

        </match>
     </magic>
     <glob pattern="*.tga"/>
     <glob pattern="*.icb"/>
     <glob pattern="*.vda"/>
     <!-- <glob pattern="*.vst"/> --> <!-- conflicting with application/vnd.visio-->
  </mime-type>

  <mime-type type="application/x-abiword">
    <glob pattern="*.abw"/>

				{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:           "DCBT",
		auxType:        auxInt64,
		argLen:         2,
		hasSideEffects: true,
		asm:            ppc64.ADCBT,
		reg: regInfo{
			inputs: []inputInfo{