VADD	V2.S4, V0.S4, V0.S4
	VADD	V1.S4, V20.S4, V20.S4
	CBNZ	R3, blockloop

sha1ret:

	VST1.P	[V0.S4], 16(R0)                               // store hash value H(dcba)
	FMOVS	F20, (R0)                                     // store hash value H(e)

	VLD1.P	16(R1), [V6.B16]                            // load 16bytes message
	VLD1.P	16(R1), [V7.B16]                            // load 16bytes message
	VMOV	V0.B16, V2.B16                              // backup: VO h(dcba)
	VMOV	V1.B16, V3.B16                              // backup: V1 h(hgfe)
	VMOV	V2.B16, V8.B16
	VREV32	V4.B16, V4.B16                              // prepare for using message in Byte format
	VREV32	V5.B16, V5.B16

	SRDCC	$3, DWORDS, OCTWORDS	// 64 byte chunks?
	MOVD	$16, IDX16
	BEQ	lt64gt8			// < 64 bytes

	// Prepare for moves of 64 bytes at a time.

forward64setup:
	DCBTST	(TGT)			// prepare data cache
	DCBT	(SRC)
	MOVD	OCTWORDS, CTR		// Number of 64 byte chunks
	MOVD	$32, IDX32
	MOVD	$48, IDX48
	PCALIGN	$16

forward64:
	LXVD2X	(R0)(SRC), VS32		// load 64 bytes
	LXVD2X	(IDX16)(SRC), VS33
	LXVD2X	(IDX32)(SRC), VS34

	ADDC  R20, R4, R6	// R6 = x[i] + c
	CMP   R11, $0		// If z_len was 1, we are done
	MOVD  R6, 0(R10)	// z[i]
	BEQ   final

	// We will read 4 elements per iteration
	SRDCC $2, R11, R9	// R9 = z_len/4
	DCBT  (R8)
	MOVD  R9, CTR		// Set up the loop counter
	BEQ   tail		// If R9 = 0, we can't use the loop
	PCALIGN $16

loop:
	MOVD  8(R8), R20	// R20 = x[i]
	MOVD  16(R8), R21	// R21 = x[i+1]

	{0x5255866ad6ef28a6, 0x790ef2b16a745a41, "Nepal premier won't resign.", "crc\x02s\xba\x84\x84\xbb\xcd]\xef\xcbf\x11R\xbfh\xde\xc9", "crc\x02`&\x9aR\xe1\xb7\xfee6\x13ُ\x06_\xbd\x9a"},

	ASUBME
	ASUBMECC
	ASUBMEVCC
	ASUBMEV
	ASUBV
	ASUBE
	ASUBECC
	ASUBEV
	ASUBEVCC
	ASUBZE
	ASUBZECC
	ASUBZEVCC
	ASUBZEV
	ASYNC
	AXOR
	AXORCC
	AXORIS

	ADCBF
	ADCBI
	ADCBST
	ADCBT
	ADCBTST
	ADCBZ
	AEIEIO
	AICBI
	AISYNC
	APTESYNC
	ATLBIE
	ATLBIEL
	ATLBSYNC
	ATW

	ASYSCALL
	AWORD

	ARFCI

	AFCPSGN

// Prefetch instructions (TH specified using aux field)
// For DCBT Ra,Rb,TH, A value of TH indicates:
//     0, hint this cache line will be used soon. (PrefetchCache)
//     16, hint this cache line will not be used for long. (PrefetchCacheStreamed)
// See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/
(PrefetchCache ptr mem)          => (DCBT ptr mem [0])
(PrefetchCacheStreamed ptr mem)  => (DCBT ptr mem [16])

		// Prefetch instruction
		// Do prefetch of address generated with arg0 and arg1 with option aux. arg0=addr,arg1=memory, aux=option.
		{name: "DCBT", argLength: 2, aux: "Int64", reg: prefreg, asm: "DCBT", hasSideEffects: true},

		// Store bytes in the reverse endian order of the arch into arg0.
		// These are indexed stores with no offset field in the instruction so the auxint fields are not used.

	JEQ		done
	ADDQ		dataPtr, numBytes		// point numBytes to end of input buffer
	VMOVDQU		(0*16)(digestPtr), state0	// load initial hash values and reorder
	VMOVDQU		(1*16)(digestPtr), state1	// DCBA, HGFE -> ABEF, CDGH
	PSHUFD		$0xb1, state0, state0		// CDAB
	PSHUFD		$0x1b, state1, state1		// EFGH
	VMOVDQA		state0, m4
	PALIGNR		$8, state1, state0		// ABEF
	PBLENDW		$0xf0, m4, state1		// CDGH

		case ALWAR,
			ALBAR,
			ASTBCCC,
			ASTWCCC,
			AEIEIO,
			AICBI,
			AISYNC,
			ATLBIE,
			ATLBIEL,
			ASLBIA,
			ASLBIE,
			ASLBMFEE,
			ASLBMFEV,
			ASLBMTE,
			ADCBF,
			ADCBI,
			ADCBST,
			ADCBT,
			ADCBTST,
			ADCBZ,
			ASYNC,
			ATLBSYNC,
			APTESYNC,
			ALWSYNC,
			ATW,
			AWORD,
			ARFI,
			ARFCI,
			ARFID,
			AHRFID: