VWSUBWX		X10, V2, V4, V3			// ERROR "invalid vector mask register"
	VWCVTXXV	V2, V1, V3			// ERROR "invalid vector mask register"
	VWCVTUXXV	V2, V1, V3			// ERROR "invalid vector mask register"
	VZEXTVF2	V2, V3, V4			// ERROR "invalid vector mask register"
	VSEXTVF2	V2, V3, V4			// ERROR "invalid vector mask register"
	VZEXTVF4	V2, V3, V4			// ERROR "invalid vector mask register"

    // Input tensors
    const std::vector<std::pair<string, Tensor>>& input_pairs,
    // Output tensors
    const std::vector<string>& output_tensor_names, TF_Tensor** c_outputs,
    // Target nodes
    const std::vector<string>& target_oper_names, TF_Buffer* run_metadata,
    TF_Status* status) {
  const int noutputs = output_tensor_names.size();
  std::vector<Tensor> outputs(noutputs);
  Status result;

  }

  // Checks the expected result of shape inference for the given `op`.
  void CheckOutputShapes(
      TFE_Op* op,
      const std::vector<absl::optional<std::vector<int64_t>>>& input_shapes_vec,
      const std::vector<TF_Tensor*>& input_tensors,
      const absl::optional<std::vector<int64_t>>& expected_shape) {
    // Create input_shapes.
    TF_ShapeAndTypeList* input_shapes =

        .createTestSuite();
  }

  // We are testing Vector / testing our tests on Vector.
  @SuppressWarnings("JdkObsolete")
  private Test testsForVector() {
    return ListTestSuiteBuilder.using(
            new TestStringListGenerator() {
              @Override
              protected List<String> create(String[] elements) {
                return new Vector<>(MinimalCollection.of(elements));
              }
            })

	VWMACCUSVX	V2, X10, V0, V3			// d76125f8

	// 31.11.15: Vector Integer Merge Instructions
	VMERGEVVM	V1, V2, V0, V3			// d781205c
	VMERGEVXM	X10, V2, V0, V3			// d741255c
	VMERGEVIM	$15, V2, V0, V3			// d7b1275c

	// 31.11.16: Vector Integer Move Instructions
	VMVVV		V2, V3				// d701015e
	VMVVX		X10, V3				// d741055e
	VMVVI		$15, V3				// d7b1075e

	// 31.12.1: Vector Single-Width Saturating Add and Subtract

            if (mechs != null) {
                final ASN1EncodableVector vector = new ASN1EncodableVector();
                for (final ASN1ObjectIdentifier mech : mechs) {
                    vector.add(mech);
                }
                fields.add(new DERTaggedObject(true, 0, new DERSequence(vector)));
            }
            final int ctxFlags = getContextFlags();
            if (ctxFlags != 0) {

  std::vector<tensorflow::string> tensor_id_data;
};

struct TF_ImportGraphDefResults {
  std::vector<TF_Output> return_tensors;
  std::vector<TF_Operation*> return_nodes;
  std::vector<const char*> missing_unused_key_names;
  std::vector<int> missing_unused_key_indexes;

  // Backing memory for missing_unused_key_names values.
  std::vector<tensorflow::string> missing_unused_key_names_data;

	MOVL (AX)(X0*1), AX             // ERROR "invalid instruction"
	MOVL (AX)(Y0*1), AX             // ERROR "invalid instruction"
	// VSIB/VM is invalid without vector index.
	// TODO(quasilyte): improve error message (#21860).
	// "invalid VSIB address (missing vector index)"
	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"
	// AVX2GATHER mask/index/dest #UD cases.

		}
	}
	if opd, ok := riscv64SpecialOperand[name]; ok {
		return opd
	}
	return riscv.SPOP_END
}

// RISCV64ValidateVectorType reports whether the given configuration is a
// valid vector type.
func RISCV64ValidateVectorType(vsew, vlmul, vtail, vmask int64) error {
	_, err := riscv.EncodeVectorType(vsew, vlmul, vtail, vmask)
	return err

        assertArrayEquals(result1, result2);
    }

    @Test
    void testHMACT64WithKnownTestVector() throws NoSuchAlgorithmException {
        // Test with known test vector
        // Using test vector from RFC 2104 adapted for HMACT64
        byte[] key = new byte[16];
        Arrays.fill(key, (byte) 0x0b);
        byte[] data = "Hi There".getBytes();