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Results 11 - 19 of 19 for SLW (0.05 sec)
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src/cmd/compile/internal/ssa/_gen/S390XOps.go
{name: "SLW", argLength: 2, reg: sh21, asm: "SLW"}, // arg0 << arg1, shift amount is mod 64 {name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "UInt8"}, // arg0 << auxint, shift amount 0-63 {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "UInt8"}, // arg0 << auxint, shift amount 0-31
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
test/codegen/memcombine.go
// s390x:`MOVHZ\s\(.*\),`,-`OR`,-`ORW`,-`SLD`,-`SLW` return binary.BigEndian.Uint16(b) } func load_be16_idx(b []byte, idx int) uint16 { // amd64:`ROLW\s\$8`,-`MOVB`,-`OR` // arm64:`REV16W`,`MOVHU\s\(R[0-9]+\)\(R[0-9]+\),`,-`MOVB` // ppc64le:`MOVHBR`,-`MOVBZ` // ppc64:`MOVHZ`,-`MOVBZ` // s390x:`MOVHZ\s\(.*\)\(.*\*1\),`,-`OR`,-`ORW`,-`SLD`,-`SLW` return binary.BigEndian.Uint16(b[idx:]) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 21 19:45:41 UTC 2024 - 29.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/doc.go
Examples: SRAD $8,R3,R4 => sradi r4,r3,8 SRD $8,R3,R4 => rldicl r4,r3,56,8 SLD $8,R3,R4 => rldicr r4,r3,8,55 SRAW $16,R4,R5 => srawi r5,r4,16 SRW $40,R4,R5 => rlwinm r5,r4,0,0,31 SLW $12,R4,R5 => rlwinm r5,r4,12,0,19 Some non-simple shifts have operands in the Go assembly which don't map directly onto operands in the PPC64 assembly. When an operand in a shift instruction in the
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 11.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
MODUD R3, R4, R5 // 7ca41a12 MODUW R3, R4, R5 // 7ca41a16 MODSD R3, R4, R5 // 7ca41e12 MODSW R3, R4, R5 // 7ca41e16 SLW $8, R3, R4 // 5464402e SLW R3, R4, R5 // 7c851830 SLWCC R3, R4 // 7c841831 SLD $16, R3, R4 // 786483e4 SLD R3, R4, R5 // 7c851836
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 334.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
typ := &b.Func.Config.Types // match: (Lsh32x16 x y) // cond: shiftIsBounded(v) // result: (SLW x y) for { x := v_0 y := v_1 if !(shiftIsBounded(v)) { break } v.reset(OpPPC64SLW) v.AddArg2(x, y) return true } // match: (Lsh32x16 <t> x y) // result: (ISEL [2] (SLW <t> x y) (MOVDconst [0]) (CMPconst [0] (ANDconst [0xFFE0] y))) for { t := v.Type x := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
// Lower bounded shifts first. No need to check shift value. (Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y) (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
o2 = LOP_IRR(opl, uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.From.Offset)&0xFFFF) case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add, add $s34con,r1 ==> addis+ori+slw+ori+add */ if p.To.Reg == REGTMP || p.Reg == REGTMP { c.ctxt.Diag("can't synthesize large constant\n%v", p) } d := c.vregoff(&p.From) r := int(p.Reg) if r == 0 { r = int(p.To.Reg) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SLW", argLen: 2, asm: ppc64.ASLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)