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Results 11 - 20 of 30 for Rem (0.02 sec)
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src/main/assemblies/files/fess.in.bat
REM SSL truststore for certificate validation over https REM FESS_JAVA_OPTS=%FESS_JAVA_OPTS% -Djavax.net.ssl.trustStore=/tech/elastic/config/truststore.jks REM FESS_JAVA_OPTS=%FESS_JAVA_OPTS% -Djavax.net.ssl.trustStorePassword=changeit REM Causes the JVM to dump its heap on OutOfMemory. REM set FESS_JAVA_OPTS=%FESS_JAVA_OPTS% -XX:+HeapDumpOnOutOfMemoryError
Registered: Thu Sep 04 12:52:25 UTC 2025 - Last Modified: Sun Jan 15 06:32:15 UTC 2023 - 4.2K bytes - Viewed (0) -
android/guava/src/com/google/common/primitives/UnsignedLongs.java
* that floor(floor(x)/i) == floor(x/i) for any real x and integer i != 0. The proof is not * quite trivial. */ long quotient = ((dividend >>> 1) / divisor) << 1; long rem = dividend - quotient * divisor; return rem - (compare(rem, divisor) >= 0 ? divisor : 0); } /** * Returns the unsigned {@code long} value represented by the given decimal string. *
Registered: Fri Sep 05 12:43:10 UTC 2025 - Last Modified: Mon Aug 11 19:31:30 UTC 2025 - 17.8K bytes - Viewed (0) -
src/main/java/jcifs/internal/smb2/ServerMessageBlock2.java
Registered: Sun Sep 07 00:10:21 UTC 2025 - Last Modified: Sun Aug 31 08:00:57 UTC 2025 - 24K bytes - Viewed (0) -
src/cmd/asm/internal/arch/mips.go
mips.ACMPGTF, mips.ACMPGTD: return true } return false } // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling. func IsMIPSMUL(op obj.As) bool { switch op { case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU, mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 04 19:06:44 UTC 2020 - 1.7K bytes - Viewed (0) -
src/test/java/jcifs/internal/smb2/ServerMessageBlock2Test.java
// size8(10, 2): rem = 10%8 - 2 = 2 - 2 = 0, returns 10 assertEquals(10, ServerMessageBlock2.size8(10, 2)); // size8(18, 2): rem = 18%8 - 2 = 2 - 2 = 0, returns 18 assertEquals(18, ServerMessageBlock2.size8(18, 2)); // size8(17, 2): rem = 17%8 - 2 = 1 - 2 = -1, rem = 8 + (-1) = 7, returns 17 + 8 - 7 = 18
Registered: Sun Sep 07 00:10:21 UTC 2025 - Last Modified: Thu Aug 14 05:31:44 UTC 2025 - 39.5K bytes - Viewed (0) -
src/archive/tar/strconv.go
rec, nl, rem := rest[:n-1], rest[n-1:n], rest[n:] if nl != "\n" { return "", "", s, ErrHeader } // The first equals separates the key from the value. k, v, ok = strings.Cut(rec, "=") if !ok { return "", "", s, ErrHeader } if !validPAXRecord(k, v) { return "", "", s, ErrHeader } return k, v, rem, nil }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Mon Sep 08 17:08:20 UTC 2025 - 9.1K bytes - Viewed (0) -
src/main/webapp/css/admin/html5shiv.min.js
/** * @preserve HTML5 Shiv 3.7.3 | @afarkas @jdalton @jon_neal @rem | MIT/GPL2 Licensed */
Registered: Thu Sep 04 12:52:25 UTC 2025 - Last Modified: Sun Dec 31 23:16:54 UTC 2017 - 2.7K bytes - Viewed (0) -
guava/src/com/google/common/math/LongMath.java
@SuppressWarnings("fallthrough") public static long divide(long p, long q, RoundingMode mode) { checkNotNull(mode); long div = p / q; // throws if q == 0 long rem = p - q * div; // equals p % q if (rem == 0) { return div; } /* * Normal Java division rounds towards 0, consistently with RoundingMode.DOWN. We just have to
Registered: Fri Sep 05 12:43:10 UTC 2025 - Last Modified: Fri Aug 29 16:20:07 UTC 2025 - 46.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// } DIV R18, R22 // 02d2001a DIVU R14, R9 // 012e001b DIVV R8, R13 // 01a8001e DIVVU R16, R19 // 0270001f // LREM rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } REM R18, R22 // 02d2001a REMU R14, R9 // 012e001b REMV R8, R13 // 01a8001e REMVU R16, R19 // 0270001f // LSHW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MULU R4, R5 // a5101c00 MULU R4, R5, R6 // a6101c00 MULH R4, R5 // a5901c00 MULH R4, R5, R6 // a6901c00 MULHU R4, R5 // a5101d00 MULHU R4, R5, R6 // a6101d00 REM R4, R5 // a5902000 REM R4, R5, R6 // a6902000 REMU R4, R5 // a5902100 REMU R4, R5, R6 // a6902100 DIV R4, R5 // a5102000 DIV R4, R5, R6 // a6102000 DIVU R4, R5 // a5102100
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Sep 04 19:24:25 UTC 2025 - 35.5K bytes - Viewed (0)