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Results 11 - 20 of 25 for LoweredGetClosurePtr (0.68 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    			},
    			clobberFlags:   true,
    			faultOnNilArg0: true,
    			faultOnNilArg1: true,
    		},
    
    		// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
    		// and sorts it to the very beginning of the block to prevent other
    		// use of R26 (arm64.REGCTXT, the closure pointer)
    		{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R26")}}, zeroWidth: true},
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		// Lowering pass-throughs
    		{name: "LoweredNilCheck", argLength: 2, faultOnNilArg0: true, nilCheck: true, reg: regInfo{inputs: []regMask{gpspMask}}}, // arg0=ptr,arg1=mem, returns void.  Faults if ptr is nil.
    		{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{regCtxt}}},                                                // scheduler ensures only at beginning of entry block
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
    (IsInBounds idx len) => (SGTU len idx)
    (IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len))
    
    // pseudo-ops
    (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
    (GetCallerSP ...) => (LoweredGetCallerSP ...)
    (GetCallerPC ...) => (LoweredGetCallerPC ...)
    
    (If cond yes no) => (NE (MOVBUreg <typ.UInt64> cond) yes no)
    
    // Write barrier.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (IsNonNil ptr) => (SGTU ptr (MOVWconst [0]))
    (IsInBounds idx len) => (SGTU len idx)
    (IsSliceInBounds idx len) => (XORconst [1] (SGTU idx len))
    
    // pseudo-ops
    (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
    (GetCallerSP ...) => (LoweredGetCallerSP ...)
    (GetCallerPC ...) => (LoweredGetCallerPC ...)
    
    (If cond yes no) => (NE cond yes no)
    
    // Write barrier.
    (WB ...) => (LoweredWB ...)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    // Checks
    (IsNonNil ...) => (SNEZ ...)
    (IsInBounds ...) => (Less64U ...)
    (IsSliceInBounds ...) => (Leq64U ...)
    
    // Trivial lowering
    (NilCheck ...) => (LoweredNilCheck ...)
    (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
    (GetCallerSP ...) => (LoweredGetCallerSP ...)
    (GetCallerPC ...) => (LoweredGetCallerPC ...)
    
    // Write barrier.
    (WB ...) => (LoweredWB ...)
    
    // Publication barrier as intrinsic
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/AMD64Ops.go

    		// Pseudo-ops
    		{name: "LoweredGetG", argLength: 1, reg: gp01}, // arg0=mem
    		// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
    		// and sorts it to the very beginning of the block to prevent other
    		// use of DX (the closure pointer)
    		{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("DX")}}, zeroWidth: true},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Aug 04 16:40:24 UTC 2023
    - 98K bytes
    - Viewed (1)
  7. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
    (IsInBounds idx len) => (SGTU len idx)
    (IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len))
    
    // pseudo-ops
    (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
    (GetCallerSP ...) => (LoweredGetCallerSP ...)
    (GetCallerPC ...) => (LoweredGetCallerPC ...)
    
    (If cond yes no) => (NE cond yes no)
    
    // Write barrier.
    (WB ...) => (LoweredWB ...)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    // Lowering calls
    (StaticCall ...) => (CALLstatic ...)
    (ClosureCall ...) => (CALLclosure ...)
    (InterCall ...) => (CALLinter ...)
    (TailCall ...) => (CALLtail ...)
    
    // Miscellaneous
    (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
    (GetCallerSP ...) => (LoweredGetCallerSP ...)
    (GetCallerPC ...) => (LoweredGetCallerPC ...)
    (IsNonNil ptr) => (NotEqual (CMPconst [0] ptr))
    (IsInBounds idx len) => (LessThan (CMPU idx len))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/debug.go

    				return !opcodeTable[v.Op].zeroWidth
    			} else {
    				return v.Op == OpInitMem
    			}
    		}
    
    		// Examine the prolog portion of the block to process special
    		// zero-width ops such as Arg, Phi, LoweredGetClosurePtr (etc)
    		// whose lifetimes begin at the block starting point. In an
    		// entry block, allow for the possibility that we may see Arg
    		// ops that appear _after_ other non-zero-width operations.
    		// Example:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jun 10 19:44:43 UTC 2024
    - 58.4K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (IsSliceInBounds idx len) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len))
    (NilCheck ...) => (LoweredNilCheck ...)
    (GetG ...) => (LoweredGetG ...)
    (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
    (GetCallerSP ...) => (LoweredGetCallerSP ...)
    (GetCallerPC ...) => (LoweredGetCallerPC ...)
    (Addr {sym} base) => (MOVDaddr {sym} base)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
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