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Results 11 - 20 of 22 for GetReq (0.12 sec)
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src/internal/bytealg/compare_amd64.s
SHRQ CX, SI // move a's bit to bottom ANDQ $1, SI // mask bit LEAQ -1(SI*2), AX // 1/0 => +1/-1 RET allsame: XORQ AX, AX XORQ CX, CX CMPQ BX, DX SETGT AX // 1 if alen > blen SETEQ CX // 1 if alen == blen LEAQ -1(CX)(AX*2), AX // 1,0,-1 result RET // this works for >= 64 bytes of data. #ifndef hasAVX2 big_loop: MOVOU (SI), X0 MOVOU (DI), X1 PCMPEQB X0, X1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Aug 18 17:17:01 UTC 2022 - 4.3K bytes - Viewed (0) -
src/cmd/internal/obj/x86/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/386Ops.go
{name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL"}, // (int32)(-1) if carry is set, 0 if carry is clear. // Note: SBBW and SBBB are subsumed by SBBL {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ"}, // extract == condition from arg0 {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE"}, // extract != condition from arg0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 14 08:10:32 UTC 2023 - 45.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
{name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL"}, // (int32)(-1) if carry is set, 0 if carry is clear. // Note: SBBW and SBBB are subsumed by SBBL {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ"}, // extract == condition from arg0 {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE"}, // extract != condition from arg0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
docs/en/data/github_sponsors.yml
avatarUrl: https://avatars.githubusercontent.com/u/317045?u=f1349d5ffe84a19f324e204777859fbf69ddf633&v=4 url: https://github.com/adamghill - login: eteq avatarUrl: https://avatars.githubusercontent.com/u/346587?v=4 url: https://github.com/eteq - login: dmig avatarUrl: https://avatars.githubusercontent.com/u/388564?v=4 url: https://github.com/dmig - login: securancy
Registered: Mon Jun 17 08:32:26 UTC 2024 - Last Modified: Mon Jun 03 01:09:53 UTC 2024 - 27K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite386.go
return false } func rewriteValue386_Op386SETEQ(v *Value) bool { v_0 := v.Args[0] // match: (SETEQ (InvertFlags x)) // result: (SETEQ x) for { if v_0.Op != Op386InvertFlags { break } x := v_0.Args[0] v.reset(Op386SETEQ) v.AddArg(x) return true } // match: (SETEQ (FlagEQ)) // result: (MOVLconst [1]) for { if v_0.Op != Op386FlagEQ { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 21:05:46 UTC 2023 - 262.4K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/tools/go/analysis/passes/asmdecl/asmdecl.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 03 02:38:00 UTC 2024 - 22.8K bytes - Viewed (0) -
src/runtime/asm_386.s
TEXT ·checkASM(SB),NOSPLIT,$0-1 // check that masks<>(SB) and shifts<>(SB) are aligned to 16-byte MOVL $masks<>(SB), AX MOVL $shifts<>(SB), BX ORL BX, AX TESTL $15, AX SETEQ ret+0(FP) RET TEXT runtime·return0(SB), NOSPLIT, $0 MOVL $0, AX RET // Called from cgo wrappers, this function returns g->m->curg.stack.hi. // Must obey the gcc calling convention.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 15 15:45:13 UTC 2024 - 43.1K bytes - Viewed (0) -
src/runtime/asm_amd64.s
// func checkASM() bool TEXT ·checkASM(SB),NOSPLIT,$0-1 // check that masks<>(SB) and shifts<>(SB) are aligned to 16-byte MOVQ $masks<>(SB), AX MOVQ $shifts<>(SB), BX ORQ BX, AX TESTQ $15, AX SETEQ ret+0(FP) RET // these are arguments to pshufb. They move data down from // the high bytes of the register to the low bytes of the register. // index is how many bytes to move.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 60.4K bytes - Viewed (0)