TEXT ·a14(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ R15, AX, BX // ERROR "when dynamic linking, R15 is clobbered by a global variable access and is used here"
	RET
TEXT ·a15(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ AX, R15, BX
	ADDQ $1, R15
	RET
TEXT ·a16(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ AX, BX, R15
	ADDQ $1, R15
	RET
TEXT ·a17(SB), 0, $0-0

	// Included to simplify validation of CL that fixed that.
	MOVQ (AX), M0  // 0f6f00
	MOVQ M0, 8(SP) // 0f7f442408
	MOVQ 8(SP), M0 // 0f6f442408
	MOVQ M0, (AX)  // 0f7f00
	MOVQ M0, (BX)  // 0f7f03
	// On non-64bit arch, Go asm allowed uint32 offsets instead of int32.
	// These tests check that property for backwards-compatibility.
	MOVL 2147483648(AX), AX  // 8b8000000080
	MOVL -2147483648(AX), AX // 8b8000000080

get_tls(CX)
MOVL	g(CX), AX     // Move g into AX.
MOVL	g_m(AX), BX   // Move g.m into BX.
</pre>

<p>
The <code>get_tls</code> macro is also defined on <a href="#amd64">amd64</a>.
</p>

<p>
Addressing modes:
</p>

<ul>

<li>
<code>(DI)(BX*2)</code>: The location at address <code>DI</code> plus <code>BX*2</code>.
</li>

<li>

	"DBW": arm.C_WBIT | arm.C_PBIT,
	"DAW": arm.C_WBIT,
	"IB":  arm.C_PBIT | arm.C_UBIT,
	"IA":  arm.C_UBIT,
	"DB":  arm.C_PBIT,
	"DA":  0,
}

var armJump = map[string]bool{
	"B":    true,
	"BL":   true,
	"BX":   true,
	"BEQ":  true,
	"BNE":  true,
	"BCS":  true,
	"BHS":  true,
	"BCC":  true,
	"BLO":  true,
	"BMI":  true,
	"BPL":  true,
	"BVS":  true,
	"BVC":  true,
	"BHI":  true,
	"BLS":  true,

	VPMADD52HUQ 15(DX)(BX*2), Y31, K7, Y17             // 62e28527b58c5a0f000000
	VPMADD52HUQ Y28, Y8, K7, Y17                       // 6282bd2fb5cc
	VPMADD52HUQ Y13, Y8, K7, Y17                       // 62c2bd2fb5cd
	VPMADD52HUQ Y7, Y8, K7, Y17                        // 62e2bd2fb5cf
	VPMADD52HUQ (R8), Y8, K7, Y17                      // 62c2bd2fb508
	VPMADD52HUQ 15(DX)(BX*2), Y8, K7, Y17              // 62e2bd2fb58c5a0f000000

	VP4DPWSSD 15(DX)(BX*8), [Z2-Z5], K4, Z17           // 62e26f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z12-Z15], K4, Z17          // 62e21f4c528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z12-Z15], K4, Z17         // 62e21f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z22-Z25], K4, Z17          // 62e24f44528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z22-Z25], K4, Z17         // 62e24f44528cda0f000000

	VMOVNTDQ Y26, 15(DX)(BX*4)                         // 62617d28e7949a0f000000
	VMOVNTDQ Z18, -15(R14)(R15*1)                      // 62817d48e7943ef1ffffff
	VMOVNTDQ Z24, -15(R14)(R15*1)                      // 62017d48e7843ef1ffffff
	VMOVNTDQ Z18, -15(BX)                              // 62e17d48e793f1ffffff
	VMOVNTDQ Z24, -15(BX)                              // 62617d48e783f1ffffff

	VPDPBUSD -15(BX), X16, K2, X6                      // 62f27d0250b3f1ffffff
	VPDPBUSD X15, X28, K2, X6                          // 62d21d0250f7
	VPDPBUSD X11, X28, K2, X6                          // 62d21d0250f3
	VPDPBUSD X1, X28, K2, X6                           // 62f21d0250f1
	VPDPBUSD -15(R14)(R15*1), X28, K2, X6              // 62921d0250b43ef1ffffff
	VPDPBUSD -15(BX), X28, K2, X6                      // 62f21d0250b3f1ffffff

//	{
//		outcode($1, $2, &nullgen, 0, &$4);
//	}
	BEQ	2(PC)
	B	foo(SB) // JMP foo(SB)
	BEQ	2(PC)
	B	bar<>(SB) // JMP bar<>(SB)

//
// BX
//
//	LTYPEBX comma ireg
//	{
//		outcode($1, Always, &nullgen, 0, &$3);
//	}
	BX	(R0)

//
// BEQ
//
//	LTYPE5 comma rel
//	{
//		outcode($1, Always, &nullgen, 0, &$3);
//	}
	BEQ	1(PC)

//
// SWI
//

	VMOVDQU8 15(DX)(BX*1), K3, X31                     // 62617f0b6fbc1a0f000000
	VMOVDQU8 -7(CX)(DX*2), K3, X31                     // 62617f0b6fbc51f9ffffff
	VMOVDQU8 Y3, K4, Y6                                // 62f17f2c7fde
	VMOVDQU8 Y3, K4, 7(SI)(DI*1)                       // 62f17f2c7f9c3e07000000
	VMOVDQU8 Y3, K4, 15(DX)(BX*8)                      // 62f17f2c7f9cda0f000000