VGF2P8MULB 15(R8), X1, K7, X7                      // 62d2750fcfb80f000000
	VGF2P8MULB (BP), X1, K7, X7                        // 62f2750fcf7d00
	VGF2P8MULB X15, X7, K7, X7                         // 62d2450fcfff
	VGF2P8MULB X12, X7, K7, X7                         // 62d2450fcffc
	VGF2P8MULB X0, X7, K7, X7                          // 62f2450fcff8
	VGF2P8MULB 15(R8), X7, K7, X7                      // 62d2450fcfb80f000000

        .addEqualityGroup(parse("concurrencyLevel=15"), parse("concurrencyLevel=15"))
        .addEqualityGroup(parse("initialCapacity=7"), parse("initialCapacity=7"))
        .addEqualityGroup(parse("initialCapacity=15"), parse("initialCapacity=15"))
        .addEqualityGroup(parse("maximumSize=7"), parse("maximumSize=7"))
        .addEqualityGroup(parse("maximumSize=15"), parse("maximumSize=15"))

	VEXP2PS 99(R15)(R15*4), K1, Z1                     // 62927d49c88cbf63000000
	VEXP2PS 15(DX), K1, Z1                             // 62f27d49c88a0f000000
	VEXP2PS Z20, K1, Z9                                // 62327d49c8cc
	VEXP2PS Z9, K1, Z9                                 // 62527d49c8c9
	VEXP2PS 99(R15)(R15*4), K1, Z9                     // 62127d49c88cbf63000000
	VEXP2PS 15(DX), K1, Z9                             // 62727d49c88a0f000000

	VPCOMPRESSW Z0, K7, Z3                             // 62f2fd4f63c3
	VPCOMPRESSW Z3, K7, 15(R8)(R14*8)                  // 6292fd4f639cf00f000000
	VPCOMPRESSW Z0, K7, 15(R8)(R14*8)                  // 6292fd4f6384f00f000000
	VPCOMPRESSW Z3, K7, -15(R14)(R15*2)                // 6292fd4f639c7ef1ffffff
	VPCOMPRESSW Z0, K7, -15(R14)(R15*2)                // 6292fd4f63847ef1ffffff
	VPEXPANDB X16, K1, X6                              // 62b27d0962f0

	VMSLTVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
	VMSLTUVI	$15, V2, V4, V3			// ERROR "invalid vector mask register"
	VMSGEVI		$15, V2, V4, V3			// ERROR "invalid vector mask register"
	VMSGEUVI	$15, V2, V4, V3			// ERROR "invalid vector mask register"
	VMINUVV		V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VMINUVX		X10, V2, V4, V3			// ERROR "invalid vector mask register"

	VMSGEUVV	V1, V2, V3			// d7011172
	VMSGEUVV	V1, V2, V0, V3			// d7011170
	VMSLTVI		$15, V2, V3			// d7312776
	VMSLTVI		$15, V2, V0, V3			// d7312774
	VMSLTUVI	$15, V2, V3			// d7312772
	VMSLTUVI	$15, V2, V0, V3			// d7312770
	VMSGEVI		$15, V2, V3			// d731277e
	VMSGEVI		$15, V2, V0, V3			// d731277c
	VMSGEUVI	$15, V2, V3			// d731277a
	VMSGEUVI	$15, V2, V0, V3			// d7312778

	// 31.11.9: Vector Integer Min/Max Instructions

	VBROADCASTI64X2 15(R8)(R14*8), K5, Z3              // 6292fd4d5a9cf00f000000
	VBROADCASTI64X2 -15(R14)(R15*2), K5, Z3            // 6292fd4d5a9c7ef1ffffff
	VBROADCASTI64X2 15(R8)(R14*8), K5, Z5              // 6292fd4d5aacf00f000000
	VBROADCASTI64X2 -15(R14)(R15*2), K5, Z5            // 6292fd4d5aac7ef1ffffff
	VCVTPD2QQ X15, K7, X0                              // 62d1fd0f7bc7

        assertFalse(matcher.matches("1.5"));
        assertTrue(matcher.matches("1.5.2"));
        assertFalse(matcher.matches("[1.4,1.5)"));
        assertFalse(matcher.matches("[1.5,1.5.2)"));
        assertFalse(matcher.matches("(1.5.2,1.6)"));
        assertTrue(matcher.matches("(1.4,1.5.2]"));
        assertTrue(matcher.matches("(1.5,)"));
        assertEquals("1.5.2", matcher.toString());

	VP4DPWSSD 15(DX)(BX*8), [Z2-Z5], K4, Z17           // 62e26f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z12-Z15], K4, Z17          // 62e21f4c528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z12-Z15], K4, Z17         // 62e21f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z22-Z25], K4, Z17          // 62e24f44528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z22-Z25], K4, Z17         // 62e24f44528cda0f000000

	VPOPCNTD -15(R14)(R15*1), K5, Y26                  // 62027d2d55943ef1ffffff
	VPOPCNTD -15(BX), K5, Y26                          // 62627d2d5593f1ffffff
	VPOPCNTD Y22, K5, Y30                              // 62227d2d55f6
	VPOPCNTD Y3, K5, Y30                               // 62627d2d55f3
	VPOPCNTD Y15, K5, Y30                              // 62427d2d55f7