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Results 131 - 140 of 232 for stride_w (0.17 sec)

  1. tensorflow/compiler/mlir/tensorflow/transforms/optimize.td

    // with the value in Mul.
    def FuseMulAndConv2D :
      Pat<(TF_MulOp:$mul (TF_Conv2DOp:$conv $input,
                              (Arith_ConstantOp:$filter F32ElementsAttr:$filter_value),
                              $strides, $use_cudnn, $padding, $explicit_padding,
                              IsDataFormatNHWC:$data_format, $dilations),
                         (Arith_ConstantOp:$multiplier F32ElementsAttr:$mul_value)),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 22 07:31:23 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_weights.mlir

        %0 = "tf.Conv2D"(%arg0, %cst_1) {attr_map = "0:strides,1:use_cudnn_on_gpu,2:padding,3:explicit_paddings,4:dilations", data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true} : (tensor<1x3x4x3xf32>, tensor<2x3x3x512xf32>) -> tensor<*xf32>
        // Dequantize added before BiasAdd.
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 42K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/quantization/tensorflow/tests/tf_to_quant_4bit.mlir

      %rst = "tf.Conv2D"(%arg, %fq) {T = "tfdtype$DT_FLOAT", data_format = "NHWC", dilations = [1, 2, 3, 1], padding = "SAME", strides = [1, 4, 5, 1]} : (tensor<256x32x32x3xf32>, tensor<3x3x3x16xf32>) -> tensor<256x8x7x16xf32>
      func.return %rst : tensor<256x8x7x16xf32>
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9.4K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nchw.mlir

      %1 = "tf.Transpose"(%arg0, %0) : (tensor<1x3x32x32xf32>, tensor<4xi32>) -> tensor<1x32x32x3xf32>
    
      // Compute in NHWC
      %2 = "tf.Conv2D"(%1, %arg1)
        {
          data_format = "NHWC",
          padding = "SAME",
          strides = [1, 1, 1, 1],
          dilations = [1, 1, 1, 1]
        } : (tensor<1x32x32x3xf32>, tensor<1x1x3x8xf32>) -> tensor<1x32x32x8xf32>
    
      // Convert result back: NHWC -> NCHW
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Mar 24 05:47:26 UTC 2022
    - 1.3K bytes
    - Viewed (0)
  5. src/image/draw/draw_test.go

    	s[2] = c1.B
    	s[3] = c1.A
    }
    
    func (p *slowestRGBA) PixOffset(x, y int) int {
    	return (y-p.Rect.Min.Y)*p.Stride + (x-p.Rect.Min.X)*4
    }
    
    func convertToSlowestRGBA(m image.Image) *slowestRGBA {
    	if rgba, ok := m.(*image.RGBA); ok {
    		return &slowestRGBA{
    			Pix:    append([]byte(nil), rgba.Pix...),
    			Stride: rgba.Stride,
    			Rect:   rgba.Rect,
    		}
    	}
    	rgba := image.NewRGBA(m.Bounds())
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jul 20 18:07:05 UTC 2023
    - 26K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tensorflow/tests/mlir2graphdef/unique_output_name.mlir

        %0:2 = tf_executor.graph {
          %outputs:2, %control = tf_executor.island wraps "tf.MaxPoolWithArgmax"(%arg0) {T = f32, Targmax = i32, include_batch_in_index = false, ksize = [1, 2, 2, 1], padding = "SAME", strides = [1, 2, 2, 1]} : (tensor<2x4x2x2xf32>) -> (tensor<2x2x1x2xf32>, tensor<2x2x1x2xi32>)
          tf_executor.fetch %outputs#1, %outputs#0 : tensor<2x2x1x2xi32>, tensor<2x2x1x2xf32>
        }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Mar 25 12:28:56 UTC 2022
    - 1.5K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_move_transposes_end.mlir

      // must use NCHW data format with updated kernel size and strides.
    
      // CHECK: %[[RES_PERM:.*]] = "tf.Const"() <{value = dense<[0, 2, 3, 1]> : tensor<4xi32>}>
      // CHECK: %[[MAX_POOL:[0-9]*]] = "tf.MaxPool"(%arg0) <{data_format = "NCHW", ksize = [1, 1, 3, 3], padding = "SAME", strides = [1, 1, 2, 2]}> : (tensor<1x64x112x112xf32>) -> tensor<1x64x56x56xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9.5K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/quantization/tensorflow/tests/prepare_quantize_ptq.mlir

        %2 = "tf.Conv2D"(%1, %0) {attr_map = "0:strides,1:use_cudnn_on_gpu,2:padding,3:explicit_paddings,4:dilations", data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true} : (tensor<1x3x4x3xf32>, tensor<2x3x3x2xf32>) -> tensor<*xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Feb 01 10:21:29 UTC 2023
    - 9.1K bytes
    - Viewed (0)
  9. src/image/internal/imageutil/impl.go

    	y0 := r.Min.Y - dst.Rect.Min.Y
    	y1 := r.Max.Y - dst.Rect.Min.Y
    	switch src.SubsampleRatio {
    
    	case image.YCbCrSubsampleRatio444:
    		for y, sy := y0, sp.Y; y != y1; y, sy = y+1, sy+1 {
    			dpix := dst.Pix[y*dst.Stride:]
    			yi := (sy-src.Rect.Min.Y)*src.YStride + (sp.X - src.Rect.Min.X)
    
    			ci := (sy-src.Rect.Min.Y)*src.CStride + (sp.X - src.Rect.Min.X)
    			for x := x0; x != x1; x, yi, ci = x+4, yi+1, ci+1 {
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat Mar 10 17:50:11 UTC 2018
    - 7.4K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/quantization/tensorflow/passes/quantized_function_library_tf_drq.mlir

        %3 = "tf.Sub"(%2, %filter_zp) : (tensor<*xi32>, tensor<*xi32>) -> tensor<*xi32>
    
        %5 = "tf.Conv2D"(%1, %3) {
          padding = "VALID", strides = [1, 1, 1, 1],
          attr_map = "strides:0,use_cudnn_on_gpu:1,padding:2,explicit_paddings:3,dilations:4"
        } : (tensor<*xi32>, tensor<*xi32>) -> tensor<*xi32>
        func.return %5 : tensor<*xi32>
      }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Mar 03 15:43:38 UTC 2023
    - 12.2K bytes
    - Viewed (0)
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