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Results 121 - 130 of 480 for MUL (0.02 sec)
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tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf_collective.cc
StringRef reduce_op = all_reduce.getReduceOp(); StringRef merge_op, final_op; if (reduce_op == "Add") { merge_op = "Add"; final_op = "Id"; } else if (reduce_op == "Mul") { merge_op = "Mul"; final_op = "Id"; } else if (reduce_op == "Min") { merge_op = "Min"; final_op = "Id"; } else if (reduce_op == "Max") { merge_op = "Max"; final_op = "Id";
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 16K bytes - Viewed (0) -
platforms/core-configuration/kotlin-dsl/src/main/kotlin/org/gradle/kotlin/dsl/execution/KotlinGrammar.kt
import org.jetbrains.kotlin.lexer.KtTokens.GTEQ import org.jetbrains.kotlin.lexer.KtTokens.LBRACKET import org.jetbrains.kotlin.lexer.KtTokens.LT import org.jetbrains.kotlin.lexer.KtTokens.LTEQ import org.jetbrains.kotlin.lexer.KtTokens.MUL import org.jetbrains.kotlin.lexer.KtTokens.NULL_KEYWORD import org.jetbrains.kotlin.lexer.KtTokens.OROR import org.jetbrains.kotlin.lexer.KtTokens.QUEST import org.jetbrains.kotlin.lexer.KtTokens.RBRACKET
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Wed Aug 02 08:06:49 UTC 2023 - 8.4K bytes - Viewed (0) -
src/go/token/token.go
IDENT // main INT // 12345 FLOAT // 123.45 IMAG // 123.45i CHAR // 'a' STRING // "abc" literal_end operator_beg // Operators and delimiters ADD // + SUB // - MUL // * QUO // / REM // % AND // & OR // | XOR // ^ SHL // << SHR // >> AND_NOT // &^ ADD_ASSIGN // += SUB_ASSIGN // -= MUL_ASSIGN // *= QUO_ASSIGN // /=
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 12:02:03 UTC 2023 - 6.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/tests/e2e/device-transform-nnapi.mlir
func.return %0 : tensor<4xf32> // CHECK: [[VAL_0:%.*]] = tfl.sub %arg0, %arg1 {fused_activation_function = "NONE"} : tensor<4xf32> // CHECK: [[VAL_1:%.*]] = tfl.mul [[VAL_0]], [[VAL_0]] {fused_activation_function = "NONE"} : tensor<4xf32 } // CHECK-LABEL: pack func.func @pack(%arg0: tensor<1xf32>, %arg1: tensor<1xf32>) -> tensor<2x1xf32> {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 1.2K bytes - Viewed (0) -
src/crypto/internal/nistec/fiat/p224.go
return e } // Sub sets e = t1 - t2, and returns e. func (e *P224Element) Sub(t1, t2 *P224Element) *P224Element { p224Sub(&e.x, &t1.x, &t2.x) return e } // Mul sets e = t1 * t2, and returns e. func (e *P224Element) Mul(t1, t2 *P224Element) *P224Element { p224Mul(&e.x, &t1.x, &t2.x) return e } // Square sets e = t * t, and returns e. func (e *P224Element) Square(t *P224Element) *P224Element {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 12 00:04:29 UTC 2022 - 3.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/convert_to_legacy_compile_and_replicate_attributes.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 22:03:30 UTC 2024 - 6.1K bytes - Viewed (0) -
test/fixedbugs/bug466.dir/b.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 02 13:43:18 UTC 2016 - 499 bytes - Viewed (0) -
src/cmd/compile/internal/syntax/operator_string.go
_ = x[OrOr-5] _ = x[AndAnd-6] _ = x[Eql-7] _ = x[Neq-8] _ = x[Lss-9] _ = x[Leq-10] _ = x[Gtr-11] _ = x[Geq-12] _ = x[Add-13] _ = x[Sub-14] _ = x[Or-15] _ = x[Xor-16] _ = x[Mul-17] _ = x[Div-18] _ = x[Rem-19] _ = x[And-20] _ = x[AndNot-21] _ = x[Shl-22] _ = x[Shr-23] } const _Operator_name = ":!<-~||&&==!=<<=>>=+-|^*/%&&^<<>>"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Apr 07 05:19:41 UTC 2021 - 1K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/tests/pick-subgraphs.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 24.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } ADD R1, R2 // LADDW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } ADD $4, R1 // LMUL rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MUL R1, R2 // LSHW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL R1, R2, R3 // LSHW rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0)