const absl::flat_hash_map<absl::string_view, int>& histogram) {
  for (const auto& pair : histogram) {
    XlaAutoClusteringSummary::OpAndCount* new_entry = result->Add();
    new_entry->set_op(std::string(pair.first));
    new_entry->set_count(pair.second);
  }

  absl::c_sort(*result, [](const XlaAutoClusteringSummary::OpAndCount& a,
                           const XlaAutoClusteringSummary::OpAndCount& b) {

  const int num_inputs = input_shapes->num_items;
  NodeDef node_def;
  tensorflow::ImmediateExecutionOperation* op = tensorflow::unwrap(tfe_op);
  node_def.set_name(op->Name());
  node_def.set_op(op->Name());
  for (int i = 0; i < num_inputs; ++i) {
    node_def.add_input("dummy_input");
  }
  OperationFromInterface(op)->Attrs().FillAttrValueMap(node_def.mutable_attr());

			return Yindir
		}
		return Yxxx

	case obj.TYPE_MEM:
		// Pseudo registers have negative index, but SP is
		// not pseudo on x86, hence REG_SP check is not redundant.
		if a.Index == REG_SP || a.Index < 0 {
			// Can't use FP/SB/PC/SP as the index register.
			return Yxxx
		}

		if vmem, ok := oclassVMem(ctxt, a); ok {
			return vmem
		}

}

int FindReturnIndex(Value val) {
  const int not_found = -1;
  for (auto user : val.getUsers()) {
    if (auto ret_op = llvm::dyn_cast<func::ReturnOp>(user)) {
      for (auto index = 0; index < ret_op->getNumOperands(); ++index) {
        if (val == ret_op->getOperand(index)) {
          return index;
        }
      }
    }
    if (auto ident_op = llvm::dyn_cast<TF::IdentityOp>(user)) {

	{1135, "", ""},
	{1136, "EDC8136I", "File is not a STREAM."},
	{1137, "EDC8137I", "STREAMS ioctl() timeout."},
	{1138, "EDC8138I", "No STREAMS resources."},
	{1139, "EDC8139I", "The message identified by set_id and msg_id is not in the message catalog."},
	{1140, "EDC8140I", "Bad message."},
	{1141, "EDC8141I", "Identifier removed."},
	{1142, "", ""},
	{1143, "", ""},
	{1144, "EDC8144I", "The link has been severed."},

		name := fmt.Sprintf("F%d", i-riscv.REG_F0)
		register[name] = int16(i)
	}

	// General registers with ABI names.
	register["ZERO"] = riscv.REG_ZERO
	register["RA"] = riscv.REG_RA
	register["SP"] = riscv.REG_SP
	register["GP"] = riscv.REG_GP
	register["TP"] = riscv.REG_TP
	register["T0"] = riscv.REG_T0
	register["T1"] = riscv.REG_T1
	register["T2"] = riscv.REG_T2
	register["S0"] = riscv.REG_S0

	IFT_SMDSICIP                  = 0x34
	IFT_SN                        = 0x38
	IFT_SONET                     = 0x27
	IFT_SONETPATH                 = 0x32
	IFT_SONETVT                   = 0x33
	IFT_SP                        = 0x39
	IFT_STARLAN                   = 0xb
	IFT_T1                        = 0x12
	IFT_TUNNEL                    = 0x3b
	IFT_ULTRA                     = 0x1d
	IFT_V35                       = 0x2d

	IFT_SMDSICIP                  = 0x34
	IFT_SN                        = 0x38
	IFT_SONET                     = 0x27
	IFT_SONETPATH                 = 0x32
	IFT_SONETVT                   = 0x33
	IFT_SP                        = 0x39
	IFT_STARLAN                   = 0xb
	IFT_T1                        = 0x12
	IFT_TUNNEL                    = 0x3b
	IFT_ULTRA                     = 0x1d
	IFT_V35                       = 0x2d

	IFT_SMDSICIP                  = 0x34
	IFT_SN                        = 0x38
	IFT_SONET                     = 0x27
	IFT_SONETPATH                 = 0x32
	IFT_SONETVT                   = 0x33
	IFT_SP                        = 0x39
	IFT_STARLAN                   = 0xb
	IFT_T1                        = 0x12
	IFT_TUNNEL                    = 0x3b
	IFT_ULTRA                     = 0x1d
	IFT_V35                       = 0x2d

    bool reuse_existing_functions, FunctionLibraryDefinition* library) {
  // name_in is copied here because name may be modified below if
  // rewrite_subgraph_fn is true.
  string name = name_in;
  call_node_def_.set_op(name);
  call_node_def_.set_name(name);
  call_node_def_.set_device(device_);

  if (rewrite_subgraph_fn) {
    std::vector<OutputTensor> arg_source_tensors(args_by_src_.size());