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Results 1 - 10 of 44 for dcmpu (0.05 sec)
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src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 334.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"MODUD", "MODUW", "MODSD", "MODSW", "EQV", "EQVCC", "EXTSB", "EXTSBCC", "EXTSH", "EXTSHCC", "FABS", "FABSCC", "FADD", "FADDCC", "FADDS", "FADDSCC", "FCMPO", "FCMPU", "FCTIW", "FCTIWCC", "FCTIWZ", "FCTIWZCC", "FDIV", "FDIVCC", "FDIVS", "FDIVSCC", "FMADD", "FMADDCC", "FMADDS", "FMADDSCC", "FMOVD", "FMOVDCC", "FMOVDU", "FMOVS",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/compile/internal/s390x/ssa.go
movd.From.Reg = v.Args[i].Reg() movd.From.Offset = 256 movd.To.Type = obj.TYPE_REG movd.To.Reg = v.Args[i].Reg() } cmpu := s.Prog(s390x.ACMPU) cmpu.From.Reg = v.Args[1].Reg() cmpu.From.Type = obj.TYPE_REG cmpu.To.Reg = v.Args[2].Reg() cmpu.To.Type = obj.TYPE_REG bne := s.Prog(s390x.ABLT) bne.To.Type = obj.TYPE_BRANCH bne.To.SetTarget(mvc) if v.AuxInt > 0 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 01:26:58 UTC 2023 - 27.1K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
"ROSBG", "RNSBGT", "RXSBGT", "ROSBGT", "RISBG", "RISBGN", "RISBGZ", "RISBGNZ", "RISBHG", "RISBLG", "RISBHGZ", "RISBLGZ", "FABS", "FADD", "FADDS", "FCMPO", "FCMPU", "CEBR", "FDIV", "FDIVS", "FMADD", "FMADDS", "FMOVD", "FMOVS", "FMSUB", "FMSUBS", "FMUL", "FMULS", "FNABS", "FNEG", "FNEGS", "LEDBR", "LDEBR", "LPDFR",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
LFDUX: "FMOVDU", STFDUX: "FMOVDU", LFSX: "FMOVS", STFSX: "FMOVS", LFSU: "FMOVSU", STFSU: "FMOVSU", LFSUX: "FMOVSU", STFSUX: "FMOVSU", CMPD: "CMP", CMPDI: "CMP", CMPW: "CMPW", CMPWI: "CMPW", CMPLD: "CMPU", CMPLDI: "CMPU", CMPLW: "CMPWU", CMPLWI: "CMPWU", MTSPR: "MOVD", MFSPR: "MOVD", // the width is ambiguous for SPRs B: "BR", BL: "CALL",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
CMP R3, R4 // 7c232000 CMP R3, R0 // 7c230000 CMP R3, R0, CR1 // CMP R3,CR1,R0 // 7ca30000 CMPU R3, R4 // 7c232040 CMPU R3, R0 // 7c230040 CMPU R3, R0, CR2 // CMPU R3,CR2,R0 // 7d230040 CMPW R3, R4 // 7c032000 CMPW R3, R0 // 7c030000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/internal/bytealg/indexbyte_ppc64x.s
CMPB R10,R5,R10 CMPB R11,R5,R11 CMPU R10,$0 CMPU R11,$0,CR1 CNTLZD R10,R10 CNTLZD R11,R11 SRD $3,R10,R3 SRD $3,R11,R11 BNE found ADD R4,R11,R4 MOVD $-1,R3 ISEL CR1EQ,R3,R4,R3 RET cmp4: // Length 4 - 7 CMPU R4,$4 BLT cmp2 MOVD $-4,R11 ADD $-4,R4,R4 _LWBEX (R0)(R3),R10 _LWBEX (R11)(R9),R11 CMPB R10,R5,R10 CMPB R11,R5,R11 CNTLZW R10,R10
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:10:29 UTC 2023 - 6.3K bytes - Viewed (0) -
src/math/pow_s390x.s
// special case Pow(+0, y < 0) = +Inf FMOVD y+8(FP), F2 FMOVD $(0.0), F4 FCMPU F2, F4 BLT posZeroLtZero //y < 0.0 BR Normal xIsNegZero: // special case Pow(-0, -Inf) = +Inf MOVD $NegInf, R4 CMPUBEQ R2, R4, zeroNegInf FMOVD y+8(FP), F2 negZeroNegY: // special case Pow(x, ±0) = 1 for any x FMOVD $(0.0), F4 FCMPU F4, F2 BLT negZeroGtZero // y > 0.0 BEQ yIsZero // y = 0.0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 16.3K bytes - Viewed (0) -
src/math/dim_s390x.s
CMPUBLT R4, R2, isMaxNaN MOVD R9, R3 AND R5, R3 // y = |y| CMPUBLT R4, R3, isMaxNaN // ±0 special cases OR R3, R2 BEQ isMaxZero FMOVD x+0(FP), F1 FMOVD y+8(FP), F2 FCMPU F2, F1 BGT +3(PC) FMOVD F1, ret+16(FP) RET FMOVD F2, ret+16(FP) RET isMaxNaN: // return NaN MOVD $NaN, R4 isPosInf: // return +Inf MOVD R4, ret+16(FP) RET isMaxZero:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 15 15:48:19 UTC 2021 - 2K bytes - Viewed (0) -
src/internal/bytealg/compare_ppc64x.s
MFVSRD VS35,R16 // move upper doublewords of A and B into GPR for comparison MFVSRD VS36,R10 CMPU R16,R10 BEQ lower SETB_CR0_NE(R3) RET PCALIGN $16 lower: VSLDOI $8,V3,V3,V3 // move lower doublewords of A and B into GPR for comparison MFVSRD VS35,R16 VSLDOI $8,V4,V4,V4 MFVSRD VS36,R10 CMPU R16,R10 SETB_CR0_NE(R3) RET PCALIGN $16 cmp8: // 8 - 15B (0 - 15B if GOPPC64_power10)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 28 17:33:20 UTC 2023 - 6.7K bytes - Viewed (0)