</li>

<li>
<code>R0.SXTB</code>
<br>
<code>R0.SXTB&lt;&lt;imm</code>:
<code>SXTB</code>: extract an 8-bit value from the low-order bits of <code>R0</code> and sign-extend it to the size of <code>R0</code>.
<code>R0.SXTB&lt;&lt;imm</code>: left shift the result of <code>R0.SXTB</code> by <code>imm</code> bits.
The <code>imm</code> value can be 0, 1, 2, 3, or 4.

				a.Reg = arm64.REG_UXTW + Rnum
			}
		case "UXTX":
			if a.Type == obj.TYPE_MEM {
				return errors.New("invalid shift for the register offset addressing mode")
			}
			a.Reg = arm64.REG_UXTX + Rnum
		case "SXTB":
			if a.Type == obj.TYPE_MEM {
				return errors.New("invalid shift for the register offset addressing mode")
			}
			a.Reg = arm64.REG_SXTB + Rnum
		case "SXTH":
			if a.Type == obj.TYPE_MEM {

	ADC R0, R2, R12                            // 4c00009a
	ADCSW R9, R21, R6                          // a602093a
	ADCS R23, R22, R22                         // d60217ba
	ADDW R5.UXTH, R8, R9                       // 0921250b
	ADD R8.SXTB<<3, R23, R14                   // ee8e288b
	ADDW $3076, R17, R3                        // 23123011
	ADDW $(3076<<12), R17, R3                  // ADDW $12599296, R17, R3           // 23127011

	SUBW	ZR<<14, R19, R13                // 6d3a1f4b
	CMP	R2.SXTH, R13                    // bfa122eb
	CMN	R1.SXTX<<2, R10                 // 5fe921ab
	CMPW	R2.UXTH<<3, R11                 // 7f2d226b
	CMNW	R1.SXTB, R9                     // 3f81212b
	ADD	R1<<1, RSP, R3                  // e367218b
	ADDW	R1<<2, R3, RSP                  // 7f48210b
	SUB	R1<<3, RSP                      // ff6f21cb