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Results 1 - 8 of 8 for SRWconst (0.13 sec)
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src/cmd/compile/internal/ssa/_gen/PPC64.rules
(ANDconst [c] (MOVWZreg x)) => (ANDconst [c&0xFFFFFFFF] x) // Eliminate unnecessary sign/zero extend following right shift (MOV(B|H|W)Zreg (SRWconst [c] (MOVBZreg x))) => (SRWconst [c] (MOVBZreg x)) (MOV(H|W)Zreg (SRWconst [c] (MOVHZreg x))) => (SRWconst [c] (MOVHZreg x)) (MOVWZreg (SRWconst [c] (MOVWZreg x))) => (SRWconst [c] (MOVWZreg x)) (MOV(B|H|W)reg (SRAWconst [c] (MOVBreg x))) => (SRAWconst [c] (MOVBreg x))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
break } c := auxIntToInt64(y.AuxInt) if !(uint64(c) <= 0xFF) { break } v.copyOf(y) return true } // match: (MOVBZreg (SRWconst [c] (MOVBZreg x))) // result: (SRWconst [c] (MOVBZreg x)) for { if v_0.Op != OpPPC64SRWconst { break } c := auxIntToInt64(v_0.AuxInt) v_0_0 := v_0.Args[0] if v_0_0.Op != OpPPC64MOVBZreg { break
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
// other bytes might contain junk so a zero extension is required if // the desired output type is larger than 1 byte. (SumBytes2 x) => (ADDW (SRWconst <typ.UInt8> x [8]) x) (SumBytes4 x) => (SumBytes2 (ADDW <typ.UInt16> (SRWconst <typ.UInt16> x [16]) x)) (SumBytes8 x) => (SumBytes4 (ADDW <typ.UInt32> (SRDconst <typ.UInt32> x [32]) x)) (Bswap64 ...) => (MOVDBR ...) (Bswap32 ...) => (MOVWBR ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
// and return mask & m. func mergePPC64RShiftMask(m, s, nbits int64) int64 { smask := uint64((1<<uint(nbits))-1) >> uint(s) return m & int64(smask) } // Combine (ANDconst [m] (SRWconst [s])) into (RLWINM [y]) or return 0 func mergePPC64AndSrwi(m, s int64) int64 { mask := mergePPC64RShiftMask(m, s, 32) if !isPPC64WordRotateMask(mask) { return 0 }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteS390X.go
// result: (FlagLT) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpS390XMOVHZreg || !(0xffff < c) { break } v.reset(OpS390XFlagLT) return true } // match: (CMPWUconst (SRWconst _ [c]) [n]) // cond: c > 0 && c < 32 && (1<<uint(32-c)) <= uint32(n) // result: (FlagLT) for { n := auxIntToInt32(v.AuxInt) if v_0.Op != OpS390XSRWconst { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 395.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "SRWconst", auxType: auxInt64, argLen: 1, asm: ppc64.ASRW, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)