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Results 1 - 9 of 9 for REG_X0 (0.11 sec)
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src/cmd/internal/obj/riscv/list.go
} func RegName(r int) string { switch { case r == 0: return "NONE" case r == REG_G: return "g" case r == REG_SP: return "SP" case REG_X0 <= r && r <= REG_X31: return fmt.Sprintf("X%d", r-REG_X0) case REG_F0 <= r && r <= REG_F31: return fmt.Sprintf("F%d", r-REG_F0) default: return fmt.Sprintf("Rgok(%d)", r-obj.RBaseRISCV) } } func opSuffixString(s uint8) string {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Feb 21 14:34:57 UTC 2024 - 959 bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm_test.go
}) } func TestRegisterListEncDec(t *testing.T) { tests := []struct { printed string reg0 int16 reg1 int16 }{ {"[R10-R13]", REG_R10, REG_R13}, {"[X0-AX]", REG_X0, REG_AX}, {"[X0-X3]", REG_X0, REG_X3}, {"[X21-X24]", REG_X21, REG_X24}, {"[Y0-Y3]", REG_Y0, REG_Y3}, {"[Y21-Y24]", REG_Y21, REG_Y24}, {"[Z0-Z3]", REG_Z0, REG_Z3}, {"[Z21-Z24]", REG_Z21, REG_Z24}, }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jul 28 19:39:51 UTC 2023 - 9.2K bytes - Viewed (0) -
src/cmd/internal/obj/x86/a.out.go
REGG = REG_R14 // g register in ABIInternal REGEXT = REG_R15 // compiler allocates external registers R15 down FREGMIN = REG_X0 + 5 // first register variable FREGEXT = REG_X0 + 15 // first external register T_TYPE = 1 << 0 T_INDEX = 1 << 1 T_OFFSET = 1 << 2 T_FCONST = 1 << 3 T_SYM = 1 << 4 T_SCONST = 1 << 5 T_64 = 1 << 6 T_GOTYPE = 1 << 7 )
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 31 20:28:39 UTC 2021 - 6.8K bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm6.go
REG_M0 + 7: return Ymr case REG_X0: return Yxr0 case REG_X0 + 1, REG_X0 + 2, REG_X0 + 3, REG_X0 + 4, REG_X0 + 5, REG_X0 + 6, REG_X0 + 7, REG_X0 + 8, REG_X0 + 9, REG_X0 + 10, REG_X0 + 11, REG_X0 + 12, REG_X0 + 13, REG_X0 + 14, REG_X0 + 15: return Yxr case REG_X0 + 16, REG_X0 + 17, REG_X0 + 18,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/cpu.go
package riscv import ( "errors" "fmt" "cmd/internal/obj" ) //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv const ( // Base register numberings. REG_X0 = obj.RBaseRISCV + iota REG_X1 REG_X2 REG_X3 REG_X4 REG_X5 REG_X6 REG_X7 REG_X8 REG_X9 REG_X10 REG_X11 REG_X12 REG_X13 REG_X14 REG_X15 REG_X16 REG_X17
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
RegisterNumber: loong64RegisterNumber, IsJump: jumpLoong64, } } func archRISCV64(shared bool) *Arch { register := make(map[string]int16) // Standard register names. for i := riscv.REG_X0; i <= riscv.REG_X31; i++ { // Disallow X3 in shared mode, as this will likely be used as the // GP register, which could result in problems in non-Go code, // including signal handlers.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 21 06:51:28 UTC 2023 - 21.3K bytes - Viewed (0) -
src/cmd/internal/obj/x86/obj6.go
case AMOVSS: if p.From.Type == obj.TYPE_FCONST { // f == 0 can't be used here due to -0, so use Float64bits if f := p.From.Val.(float64); math.Float64bits(f) == 0 { if p.To.Type == obj.TYPE_REG && REG_X0 <= p.To.Reg && p.To.Reg <= REG_X15 { p.As = AXORPS p.From = p.To break } } } fallthrough case AFMOVF, AFADDF, AFSUBF, AFSUBRF, AFMULF,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Sep 08 18:36:45 UTC 2023 - 40.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
panic(fmt.Sprintf("register out of range, want %d <= %d <= %d", min, r, max)) } return r - min } // regI returns an integer register. func regI(r uint32) uint32 { return regVal(r, REG_X0, REG_X31) } // regF returns a float register. func regF(r uint32) uint32 { return regVal(r, REG_F0, REG_F31) } // regAddr extracts a register from an Addr.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{1, x86.REG_CX, 1, "CX"}, {2, x86.REG_DX, 2, "DX"}, {3, x86.REG_BX, 3, "BX"}, {4, x86.REGSP, -1, "SP"}, {5, x86.REG_BP, 4, "BP"}, {6, x86.REG_SI, 5, "SI"}, {7, x86.REG_DI, 6, "DI"}, {8, x86.REG_X0, -1, "X0"}, {9, x86.REG_X1, -1, "X1"}, {10, x86.REG_X2, -1, "X2"}, {11, x86.REG_X3, -1, "X3"}, {12, x86.REG_X4, -1, "X4"}, {13, x86.REG_X5, -1, "X5"}, {14, x86.REG_X6, -1, "X6"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)