var ok bool
	var arngType int16
	var simdType int16
	var simdReg int16

	switch {
	case reg >= loong64.REG_V0 && reg <= loong64.REG_V31:
		simdType = loong64.LSX
		simdReg = reg - loong64.REG_V0
	case reg >= loong64.REG_X0 && reg <= loong64.REG_X31:
		simdType = loong64.LASX
		simdReg = reg - loong64.REG_X0
	default:

		}
	case "A":
		if 0 <= n && n <= 8 {
			return ppc64.REG_A0 + n, true
		}
	case "VS":
		if 0 <= n && n <= 63 {
			return ppc64.REG_VS0 + n, true
		}
	case "V":
		if 0 <= n && n <= 31 {
			return ppc64.REG_V0 + n, true
		}
	case "F":
		if 0 <= n && n <= 31 {
			return ppc64.REG_F0 + n, true
		}
	case "R":
		if 0 <= n && n <= 31 {
			return ppc64.REG_R0 + n, true
		}
	case "SPR":
		if 0 <= n && n <= 1024 {

		register[name] = int16(i)
	}
	for i := riscv.REG_F0; i <= riscv.REG_F31; i++ {
		name := fmt.Sprintf("F%d", i-riscv.REG_F0)
		register[name] = int16(i)
	}
	for i := riscv.REG_V0; i <= riscv.REG_V31; i++ {
		name := fmt.Sprintf("V%d", i-riscv.REG_V0)
		register[name] = int16(i)
	}

	// General registers with ABI names.
	register["ZERO"] = riscv.REG_ZERO
	register["RA"] = riscv.REG_RA
	register["SP"] = riscv.REG_SP

		if 0 <= n && n <= 31 {
			return arm64.REG_F0 + n, true
		}
	case "R":
		if 0 <= n && n <= 30 { // not 31
			return arm64.REG_R0 + n, true
		}
	case "V":
		if 0 <= n && n <= 31 {
			return arm64.REG_V0 + n, true
		}
	case "Z":
		if 0 <= n && n <= 31 {
			return arm64.REG_Z0 + n, true
		}
	case "P":
		if 0 <= n && n <= 15 {
			return arm64.REG_P0 + n, true
		}
	case "PN":

		}
	case "F":
		if 0 <= n && n <= 15 {
			return s390x.REG_F0 + n, true
		}
	case "R":
		if 0 <= n && n <= 15 {
			return s390x.REG_R0 + n, true
		}
	case "V":
		if 0 <= n && n <= 31 {
			return s390x.REG_V0 + n, true
		}
	}
	return 0, false