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Results 1 - 10 of 17 for REG_R31 (0.1 sec)
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src/cmd/internal/obj/loong64/list.go
obj.RegisterOpcode(obj.ABaseLoong64, Anames) } func rconv(r int) string { if r == 0 { return "NONE" } if r == REGG { // Special case. return "g" } if REG_R0 <= r && r <= REG_R31 { return fmt.Sprintf("R%d", r-REG_R0) } if REG_F0 <= r && r <= REG_F31 { return fmt.Sprintf("F%d", r-REG_F0) } if REG_FCSR0 <= r && r <= REG_FCSR31 { return fmt.Sprintf("FCSR%d", r-REG_FCSR0) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 11 20:11:34 UTC 2022 - 931 bytes - Viewed (0) -
src/cmd/internal/obj/mips/a.out.go
REG_R13 REG_R14 REG_R15 REG_R16 REG_R17 REG_R18 REG_R19 REG_R20 REG_R21 REG_R22 REG_R23 REG_R24 REG_R25 REG_R26 REG_R27 REG_R28 REG_R29 REG_R30 REG_R31 REG_F0 // must be a multiple of 32 REG_F1 REG_F2 REG_F3 REG_F4 REG_F5 REG_F6 REG_F7 REG_F8 REG_F9 REG_F10 REG_F11 REG_F12 REG_F13 REG_F14 REG_F15 REG_F16
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 7.6K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/a.out.go
REG_R13 REG_R14 REG_R15 REG_R16 REG_R17 REG_R18 REG_R19 REG_R20 REG_R21 REG_R22 REG_R23 REG_R24 REG_R25 REG_R26 REG_R27 REG_R28 REG_R29 REG_R30 REG_R31 REG_F0 // must be a multiple of 32 REG_F1 REG_F2 REG_F3 REG_F4 REG_F5 REG_F6 REG_F7 REG_F8 REG_F9 REG_F10 REG_F11 REG_F12 REG_F13 REG_F14 REG_F15 REG_F16
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/internal/obj/mips/list0.go
obj.RegisterOpcode(obj.ABaseMIPS, Anames) } func rconv(r int) string { if r == 0 { return "NONE" } if r == REGG { // Special case. return "g" } if REG_R0 <= r && r <= REG_R31 { return fmt.Sprintf("R%d", r-REG_R0) } if REG_F0 <= r && r <= REG_F31 { return fmt.Sprintf("F%d", r-REG_F0) } if REG_M0 <= r && r <= REG_M31 { return fmt.Sprintf("M%d", r-REG_M0) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 04 19:06:44 UTC 2020 - 2.5K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
REG_R13 REG_R14 REG_R15 REG_R16 REG_R17 REG_R18 REG_R19 REG_R20 REG_R21 REG_R22 REG_R23 REG_R24 REG_R25 REG_R26 REG_R27 REG_R28 REG_R29 REG_R30 REG_R31 // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32 REG_CR0LT REG_CR0GT REG_CR0EQ REG_CR0SO REG_CR1LT REG_CR1GT REG_CR1EQ REG_CR1SO REG_CR2LT REG_CR2GT REG_CR2EQ
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
// Create maps for easy lookup of instruction names etc. // Note that there is no list of names as there is for 386 and amd64. register[obj.Rconv(arm64.REGSP)] = int16(arm64.REGSP) for i := arm64.REG_R0; i <= arm64.REG_R31; i++ { register[obj.Rconv(i)] = int16(i) } // Rename R18 to R18_PLATFORM to avoid accidental use. register["R18_PLATFORM"] = register["R18"] delete(register, "R18")
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 21 06:51:28 UTC 2023 - 21.3K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/list9.go
obj.RegisterOpcode(AFIRSTGEN, GenAnames) } func rconv(r int) string { if r == 0 { return "NONE" } if r == REGG { // Special case. return "g" } if REG_R0 <= r && r <= REG_R31 { return fmt.Sprintf("R%d", r-REG_R0) } if REG_F0 <= r && r <= REG_F31 { return fmt.Sprintf("F%d", r-REG_F0) } if REG_V0 <= r && r <= REG_V31 { return fmt.Sprintf("V%d", r-REG_V0) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 15 21:12:43 UTC 2022 - 3.3K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
// ARM64RegisterShift constructs an ARM64 register with shift operation. func ARM64RegisterShift(reg, op, count int16) (int64, error) { // the base register of shift operations must be general register. if reg > arm64.REG_R31 || reg < arm64.REG_R0 { return 0, errors.New("invalid register for shift operation") } return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 29 09:04:58 UTC 2022 - 10.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/list7.go
} } func rconv(r int) string { ext := (r >> 5) & 7 if r == REGG { return "g" } switch { case REG_R0 <= r && r <= REG_R30: return fmt.Sprintf("R%d", r-REG_R0) case r == REG_R31: return "ZR" case REG_F0 <= r && r <= REG_F31: return fmt.Sprintf("F%d", r-REG_F0) case REG_V0 <= r && r <= REG_V31: return fmt.Sprintf("V%d", r-REG_V0) case r == REGSP: return "RSP"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 6K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
REG_R13 REG_R14 REG_R15 REG_R16 REG_R17 REG_R18 REG_R19 REG_R20 REG_R21 REG_R22 REG_R23 REG_R24 REG_R25 REG_R26 REG_R27 REG_R28 REG_R29 REG_R30 REG_R31 // scalar floating point REG_F0 REG_F1 REG_F2 REG_F3 REG_F4 REG_F5 REG_F6 REG_F7 REG_F8 REG_F9 REG_F10 REG_F11 REG_F12 REG_F13 REG_F14 REG_F15 REG_F16
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0)