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Results 1 - 5 of 5 for OutputInfo (0.12 sec)
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src/cmd/compile/internal/ssa/opGen.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/passes/insert_main_function.cc
// Ex: If the model output list is ["add:0", "topk:0": "topk:1"], then the // output corresponding to "topk:1" will have output_index=2 and tensor_index=1. struct OutputInfo { // The index of this output in the model output list. int32_t output_index; // The index of this output in its node. int32_t tensor_index; // The output value. Value value; };
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 16.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/op.go
scale uint8 // amd64/386 indexed load scale } type inputInfo struct { idx int // index in Args array regs regMask // allowed input registers } type outputInfo struct { idx int // index in output tuple regs regMask // allowed output registers } type regInfo struct { // inputs encodes the register restrictions for an instruction's inputs.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 22 15:29:10 UTC 2024 - 18.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/main.go
} // reg outputs s = s[:0] for i, r := range v.reg.outputs { s = append(s, intPair{countRegs(r), i}) } if len(s) > 0 { sort.Sort(byKey(s)) fmt.Fprintln(w, "outputs: []outputInfo{") for _, p := range s { r := v.reg.outputs[p.val] fmt.Fprintf(w, "{%d,%d},%s\n", p.val, r, a.regMaskComment(r)) } fmt.Fprintln(w, "},") } fmt.Fprintln(w, "},") // close reg info
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 16.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/regalloc.go
return regInfo{inputs: []inputInfo{{regs: m}}, outputs: []outputInfo{{regs: m}}} } if op == OpArgIntReg { reg := v.Block.Func.Config.intParamRegs[v.AuxInt8()] return regInfo{outputs: []outputInfo{{regs: 1 << uint(reg)}}} } if op == OpArgFloatReg { reg := v.Block.Func.Config.floatParamRegs[v.AuxInt8()] return regInfo{outputs: []outputInfo{{regs: 1 << uint(reg)}}} } if op.IsCall() {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 17:49:56 UTC 2023 - 87.2K bytes - Viewed (0)