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Results 1 - 6 of 6 for MULSSload (0.39 sec)
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src/cmd/compile/internal/ssa/_gen/386Ops.go
{name: "SUBSDload", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem {name: "MULSSload", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 14 08:10:32 UTC 2023 - 45.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite386.go
v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block config := b.Func.Config // match: (MULSSload [off1] {sym} val (ADDLconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != Op386ADDLconst {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 21:05:46 UTC 2023 - 262.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (SUBSS x (MOVLi2f y)) (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (MULSD x (MOVQi2f y)) (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (MULSS x (MOVLi2f y)) // Redirect stores to use the other register set. (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) => (MOVSDstore [off] {sym} ptr val mem)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem) // cond: is32Bit(int64(off1)+int64(off2)) // result: (MULSSload [off1+off2] {sym} val base mem) for { off1 := auxIntToInt32(v.AuxInt) sym := auxToSym(v.Aux) val := v_0 if v_1.Op != OpAMD64ADDQconst {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "MULSSload", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)