CSETM	NV, R2                                           // ERROR "invalid condition"
	LDP.P	8(R2), (R2, R3)                                  // ERROR "constrained unpredictable behavior"
	LDP.W	8(R3), (R2, R3)                                  // ERROR "constrained unpredictable behavior"
	LDP	(R1), (R2, R2)                                   // ERROR "constrained unpredictable behavior"
	LDP	(R0), (F0, F1)                                   // ERROR "invalid register pair"

	LDP	-8(RSP), (R1, R2)   // e18b7fa9
	LDP	11(RSP), (R1, R2)   // fb2f0091610b40a9
	LDP	1024(RSP), (R1, R2) // fb031091610b40a9
	LDP.W	8(RSP), (R1, R2)    // e18bc0a9
	LDP.P	8(RSP), (R1, R2)    // e18bc0a8
	LDP	-31(R0), (R1, R2)   // 1b7c00d1610b40a9
	LDP	-4(R0), (R1, R2)    // 1b1000d1610b40a9
	LDP	-8(R0), (R1, R2)    // 01887fa9
	LDP	x(SB), (R1, R2)
	LDP	x+8(SB), (R1, R2)
	LDP	8(R1), (ZR, R2)     // 3f8840a9

	STLXPW (R6, R11), (R22), R21               // c6ae3588
	//TODO STNPW 44(R1), R3, R10               // 2a8c0528
	//TODO STNP 0x108(R3), ZR, R7              // 67fc10a8
	LDP.P -384(R3), (R22, R26)                 // 7668e8a8
	LDP.W 280(R8), (R19, R11)                  // 13add1a9
	STP.P (R22, R27), 352(R0)                  // 166c96a8
	STP.W (R17, R11), 96(R8)                   // 112d86a9

better // 2) CSEL might not be constant time on all ARM processors LDP 0*16(a_ptr), (R4, R5) LDP 1*16(a_ptr), (R6, R7) LDP 2*16(a_ptr), (R8, R9) LDP 0*16(b_ptr), (R16, R17) LDP 1*16(b_ptr), (R19, R20) LDP 2*16(b_ptr), (R21, R22) CSEL EQ, R16, R4, R4 CSEL EQ, R17, R5, R5 CSEL EQ, R19, R6, R6 CSEL EQ, R20, R7, R7 CSEL EQ, R21, R8, R8 CSEL EQ, R22, R9, R9 STP (R4, R5), 0*16(res_ptr) STP (R6, R7), 1*16(res_ptr) STP (R8, R9), 2*16(res_ptr) LDP 3*16(a_ptr), (R4, R5) LDP 4*16(a_ptr), (R6, R7) LDP 5*16(a_ptr),...

	if r2 != 0 {
		// TODO: Consistency in the encoding would be nice here.
		if p.arch.InFamily(sys.ARM, sys.ARM64) {
			// Special form
			// ARM: destination register pair (R1, R2).
			// ARM64: register pair (R1, R2) for LDP/STP.
			if prefix != 0 || scale != 0 {
				p.errorf("illegal address mode for register pair")
				return
			}
			a.Type = obj.TYPE_REGREG
			a.Offset = int64(r2)
			// Nothing may follow
			return

The other extensions include <code>SXTH</code> (16-bit), <code>SXTW</code> (32-bit), and <code>SXTX</code> (64-bit).
</li>

<li>
<code>(R5, R6)</code>: Register pair for <code>LDAXP</code>/<code>LDP</code>/<code>LDXP</code>/<code>STLXP</code>/<code>STP</code>/<code>STP</code>.
</li>

</ul>

<p>
Reference: <a href="/pkg/cmd/internal/obj/arm64">Go ARM64 Assembly Instructions Reference Manual</a>
</p>