Search Options

Results per page
Sort
Preferred Languages
Advance

Results 41 - 50 of 75 for div1 (0.06 sec)

  1. src/cmd/compile/internal/ssa/_gen/genericOps.go

    	{name: "Avg64u", argLength: 2, typ: "UInt64"}, // 64-bit platforms only
    
    	// For Div16, Div32 and Div64, AuxInt non-zero means that the divisor has been proved to be not -1
    	// or that the dividend is not the most negative value.
    	{name: "Div8", argLength: 2},  // arg0 / arg1, signed
    	{name: "Div8u", argLength: 2}, // arg0 / arg1, unsigned
    	{name: "Div16", argLength: 2, aux: "Bool"},
    	{name: "Div16u", argLength: 2},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 42.6K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Select0 (Mul64uhilo x y)) => (MULHDU x y)
    (Select1 (Mul64uhilo x y)) => (MULLD x y)
    
    (Div64 [false] x y) => (DIVD x y)
    (Div64u ...) => (DIVDU ...)
    (Div32 [false] x y) => (DIVW x y)
    (Div32u ...) => (DIVWU ...)
    (Div16 [false]  x y) => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
    (Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
    (Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
    (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  3. fess-crawler/src/test/java/org/codelibs/fess/crawler/CrawlerTest.java

            crawler.crawlerContext.setMaxAccessCount(maxCount);
            crawler.crawlerContext.setNumOfThread(numOfThread);
            crawler.urlFilter.addInclude(url + ".*");
            crawler.urlFilter.addExclude(url + "/dir1/.*");
            final String sessionId = crawler.execute();
            assertEquals(maxCount, dataService.getCount(sessionId));
            dataService.delete(sessionId);
        }
    
    Registered: Wed Jun 12 15:17:51 UTC 2024
    - Last Modified: Thu Feb 22 01:36:27 UTC 2024
    - 18K bytes
    - Viewed (0)
  4. platforms/documentation/docs/src/docs/userguide/reference/ci-systems/github-actions.adoc

    [[build_github_actions]]
    = Executing Gradle builds on GitHub Actions
    
    TIP: Top engineering teams using GitHub Actions have been able to reduce CI build time by up to 90% by using the Gradle Build Cache. https://gradle.org/training/#build-cache-deep-dive[Register here] for our Build Cache training session to learn how your team can achieve similar results.
    
    Building Gradle projects doesn't stop with the developer's machine.
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Mon Apr 08 14:41:08 UTC 2024
    - 11.3K bytes
    - Viewed (0)
  5. okhttp/src/test/java/okhttp3/internal/cache/DiskLruCacheTest.kt

          filesystem.createDirectories(it)
        }
        filesystem.write(file) {
          writeUtf8(content)
        }
      }
    
      private fun generateSomeGarbageFiles() {
        val dir1 = cacheDir / "dir1"
        val dir2 = dir1 / "dir2"
        writeFile(getCleanFile("g1", 0), "A")
        writeFile(getCleanFile("g1", 1), "B")
        writeFile(getCleanFile("g2", 0), "C")
        writeFile(getCleanFile("g2", 1), "D")
    Registered: Sun Jun 16 04:42:17 UTC 2024
    - Last Modified: Mon Apr 15 14:55:09 UTC 2024
    - 75.8K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf-with-tf2xla-hlo-importer.mlir

        // CHECK-DAG-SAME: strides = dense<1> : tensor<1xi64>
        // CHECK-SAME: (tensor<2xi32>) -> tensor<1xi32>
        // CHECK: %[[DIM1:.*]] = mhlo.reshape %[[SLICE1]] : (tensor<1xi32>) -> tensor<i32>
    
        // CHECK: mhlo.dynamic_update_slice %[[ARG0]], %[[ARG1]], %[[DIM0]], %[[DIM1]]
    
        %0 = "tf.XlaDynamicUpdateSlice"(%arg0, %arg1, %arg2) : (tensor<3x4xi32>, tensor<2x2xi32>, tensor<2xi32>) -> tensor<3x4xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 06 15:32:52 UTC 2024
    - 38.6K bytes
    - Viewed (1)
  7. src/cmd/link/internal/ld/main.go

    	ownTmpDir      bool // set to true if tmp dir created by linker (e.g. no -tmpdir)
    )
    
    func init() {
    	flag.Var(&rpath, "r", "set the ELF dynamic linker search `path` to dir1:dir2:...")
    	flag.Var(&flagExtld, "extld", "use `linker` when linking in external mode")
    	flag.Var(&flagExtldflags, "extldflags", "pass `flags` to external linker")
    	flag.Var(&flagW, "w", "disable DWARF generation")
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 16:59:50 UTC 2024
    - 16.6K bytes
    - Viewed (0)
  8. platforms/core-execution/execution/src/integTest/groovy/org/gradle/internal/execution/IncrementalExecutionIntegrationTest.groovy

                validationWarningReporter,
                virtualFileSystem
            )
        }
    
        def "outputs are created"() {
            def unitOfWork = builder.withOutputDirs(
                dir1: file("outDir1"),
                dir2: file("outDir2")
            ).withOutputFiles(
                "file1": file("parent1/outFile"),
                "file2": file("parent2/outFile")
            ).withWork { ->
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Fri Mar 08 10:36:34 UTC 2024
    - 23.7K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Mul(64|32)F ...) => (FMUL(D|S) ...)
    
    (Div(64|32)F ...) => (FDIV(D|S) ...)
    
    (Div64 x y [false])  => (DIV x y)
    (Div64u ...) => (DIVU ...)
    (Div32 x y [false])  => (DIVW x y)
    (Div32u ...) => (DIVUW ...)
    (Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
    (Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
    (Div8 x y)   => (DIVW  (SignExt8to32 x)  (SignExt8to32 y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/ppc64.s

    	MULHWUCC R3, R4, R5             // 7ca41817
    	MULLDV R3, R4, R5               // 7ca41dd2
    	MULLDVCC R3, R4, R5             // 7ca41dd3
    
    	DIVD R3,R4                      // 7c841bd2
    	DIVD R3, R4, R5                 // 7ca41bd2
    	DIVW R3, R4                     // 7c841bd6
    	DIVW R3, R4, R5                 // 7ca41bd6
    	DIVDCC R3,R4, R5                // 7ca41bd3
    	DIVWCC R3,R4, R5                // 7ca41bd7
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
Back to top