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Results 1 - 10 of 17 for Avg64u (0.12 sec)

  1. src/cmd/compile/internal/ssa/_gen/generic.rules

          (Const64 <typ.UInt64> [32+umagic32(c).s-2])))
    (Div32u x (Const32 [c])) && umagicOK32(c) && config.RegSize == 8 && config.useAvg =>
      (Trunc64to32
        (Rsh64Ux64 <typ.UInt64>
          (Avg64u
            (Lsh64x64 <typ.UInt64> (ZeroExt32to64 x) (Const64 <typ.UInt64> [32]))
            (Mul64 <typ.UInt64>
              (Const64 <typ.UInt32> [int64(umagic32(c).m)])
              (ZeroExt32to64 x)))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 16 22:21:05 UTC 2024
    - 135.3K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c)
    (Select1 <t> (Sub64borrow x y c)) =>
    	(OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))
    
    // (x + y) / 2 with x>=y => (x - y) / 2 + y
    (Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
    
    (And(64|32|16|8) ...) => (AND ...)
    (Or(64|32|16|8) ...) => (OR ...)
    (Xor(64|32|16|8) ...) => (XOR ...)
    
    // shifts
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Select1 (Sub64borrow x y c)) =>
    	(OR (SLTU <typ.UInt64> x s:(SUB <typ.UInt64> x y)) (SLTU <typ.UInt64> s (SUB <typ.UInt64> s c)))
    
    // (x + y) / 2 => (x / 2) + (y / 2) + (x & y & 1)
    (Avg64u <t> x y) => (ADD (ADD <t> (SRLI <t> [1] x) (SRLI <t> [1] y)) (ANDI <t> [1] (AND <t> x y)))
    
    (Mod64 x y [false])  => (REM x y)
    (Mod64u ...) => (REMU  ...)
    (Mod32 x y [false])  => (REMW x y)
    (Mod32u ...) => (REMUW ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Select1 <t> (Sub64borrow x y c)) =>
    	(OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))
    
    // math package intrinsics
    (Abs ...) => (ABSD ...)
    
    // (x + y) / 2 with x>=y => (x - y) / 2 + y
    (Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
    
    (And(64|32|16|8) ...) => (AND ...)
    (Or(64|32|16|8) ...) => (OR ...)
    (Xor(64|32|16|8) ...) => (XOR ...)
    
    // shifts
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/genericOps.go

    	// These ops can assume arg0 >= arg1.
    	// Note: these ops aren't commutative!
    	{name: "Avg32u", argLength: 2, typ: "UInt32"}, // 32-bit platforms only
    	{name: "Avg64u", argLength: 2, typ: "UInt64"}, // 64-bit platforms only
    
    	// For Div16, Div32 and Div64, AuxInt non-zero means that the divisor has been proved to be not -1
    	// or that the dividend is not the most negative value.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 42.6K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Mod32u x y) && buildcfg.GOPPC64 >= 9 => (MODUW x y)
    (Mod32u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVWU x y)))
    
    // (x + y) / 2 with x>=y => (x - y) / 2 + y
    (Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
    
    (Mul64 ...) => (MULLD ...)
    (Mul(32|16|8) ...) => (MULLW ...)
    (Select0 (Mul64uhilo x y)) => (MULHDU x y)
    (Select1 (Mul64uhilo x y)) => (MULLD x y)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/S390X.rules

    (Mod16u x y) => (MODWU (MOVHZreg x) (MOVHZreg y))
    (Mod8   x y) => (MODW  (MOVBreg x) (MOVBreg y))
    (Mod8u  x y) => (MODWU (MOVBZreg x) (MOVBZreg y))
    
    // (x + y) / 2 with x>=y -> (x - y) / 2 + y
    (Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
    
    (And64 ...) => (AND ...)
    (And(32|16|8) ...) => (ANDW ...)
    
    (Or64 ...) => (OR ...)
    (Or(32|16|8) ...) => (ORW ...)
    
    (Xor64 ...) => (XOR ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (Mod32u ...) => (UMODW ...)
    (Mod(16|8)  x y) => (MODW  (SignExt(16|8)to32 x) (SignExt(16|8)to32 y))
    (Mod(16|8)u x y) => (UMODW (ZeroExt(16|8)to32 x) (ZeroExt(16|8)to32 y))
    
    // (x + y) / 2 with x>=y    =>    (x - y) / 2 + y
    (Avg64u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y)
    
    (And(64|32|16|8) ...) => (AND ...)
    (Or(64|32|16|8)  ...) => (OR ...)
    (Xor(64|32|16|8) ...) => (XOR ...)
    
    // unary ops
    (Neg(64|32|16|8) ...) => (NEG ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    (Select1 (NEGLflags (MOVQconst [0]))) => (FlagEQ)
    (Select1 (NEGLflags (NEGQ (SBBQcarrymask x)))) => x
    
    
    (Mul64uhilo ...) => (MULQU2 ...)
    (Div128u ...) => (DIVQU2 ...)
    
    (Avg64u ...) => (AVGQU ...)
    
    (Mod(64|32|16) [a] x y) => (Select1 (DIV(Q|L|W) [a] x y))
    (Mod8  x y) => (Select1 (DIVW  (SignExt8to16 x) (SignExt8to16 y)))
    (Mod(64|32|16)u x y) => (Select1 (DIV(Q|L|W)U x y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    		v0.AddArg(old)
    		v.AddArg4(ptr, v0, new, mem)
    		return true
    	}
    }
    func rewriteValueLOONG64_OpAvg64u(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Avg64u <t> x y)
    	// result: (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
    	for {
    		t := v.Type
    		x := v_0
    		y := v_1
    		v.reset(OpLOONG64ADDV)
    		v0 := b.NewValue0(v.Pos, OpLOONG64SRLVconst, t)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
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