| (1L << (23 - 2))
              | (1L << (29 - 2))
              | (1L << (31 - 2))
              | (1L << (37 - 2))
              | (1L << (41 - 2))
              | (1L << (43 - 2))
              | (1L << (47 - 2))
              | (1L << (53 - 2))
              | (1L << (59 - 2))
              | (1L << (61 - 2));
      // Look up n within the mask.

	XORQ R12, R14
	MOVQ R9, R12
	ANDQ R11, R12
	ORQ  R12, DI

	ADDQ R14, DX
	ADDQ R15, DX
	ADDQ DI, DX

	VPADDQ  3*32(BP), Y7, Y0
	VMOVDQU Y0, frame_YFER(SP)
	ADDQ    $(4*32), BP

	MY_VPALIGNR(Y0, Y6, Y5, 8)

	VPADDQ Y7, Y0, Y0

	MY_VPALIGNR(Y1, Y4, Y7, 8)

	VPSRLQ $1, Y1, Y2
	VPSLLQ $(64-1), Y1, Y3
	VPOR   Y2, Y3, Y3

	VPSRLQ $7, Y1, Y8

              | (1L << (23 - 2))
              | (1L << (29 - 2))
              | (1L << (31 - 2))
              | (1L << (37 - 2))
              | (1L << (41 - 2))
              | (1L << (43 - 2))
              | (1L << (47 - 2))
              | (1L << (53 - 2))
              | (1L << (59 - 2))
              | (1L << (61 - 2));
      // Look up n within the mask.

github.com/DataDog/datadog-go v3.2.0+incompatible/go.mod h1:LButxg5PwREeZtORoXG3tL4fMGNddJ+vMq1mwgfaqoQ=
github.com/IBM/sarama v1.43.2 h1:HABeEqRUh32z8yzY2hGB/j8mHSzC/HA9zlEjqFNCzSw=
github.com/IBM/sarama v1.43.2/go.mod h1:Kyo4WkF24Z+1nz7xeVUFWIuKVV8RS3wM8mkvPKMdXFQ=
github.com/VividCortex/ewma v1.2.0 h1:f58SaIzcDXrSy3kWaHNvuJgJ3Nmz59Zji6XoJR/q1ow=

      "integrity": "sha512-+5gy6OQfk+xx3q0d6jGZZC3f3KzAkXc/IanVxd1is/VIIziRqqt3ongQz0FiTUXqTk0c7aDB3OaFuKnuSoJicQ==",
      "dev": true,
      "dependencies": {
        "ajv": "^6.12.4",
        "debug": "^4.3.2",
        "espree": "^9.5.2",
        "globals": "^13.19.0",
        "ignore": "^5.2.0",
        "import-fresh": "^3.2.1",
        "js-yaml": "^4.1.0",
        "minimatch": "^3.1.2",

	ROUND_AND_SCHED_N_2(_XFER + 3*32, c, d, e, f, g, h, a, b, XDWORD3, XDWORD0, XDWORD1, XDWORD2)
	ROUND_AND_SCHED_N_3(_XFER + 3*32, b, c, d, e, f, g, h, a, XDWORD3, XDWORD0, XDWORD1, XDWORD2)

	ADDQ $4*32, SRND
	CMPQ SRND, $3*4*32
	JB   avx2_loop1

avx2_loop2:
	// w48 - w63 processed with no scheduling (last 16 rounds)
	VPADDD  0*32(TBL)(SRND*1), XDWORD0, XFER
	VMOVDQU XFER, (_XFER + 0*32)(SP)(SRND*1)

  %431 = "tf.Pack"(%7, %429) {axis = 0 : i64, device = ""} : (tensor<i32>, tensor<i32>) -> tensor<2xi32>
  %432 = "tf.Tile"(%396, %431) {device = ""} : (tensor<?x1xi64>, tensor<2xi32>) -> tensor<?x?xi64>
  %433 = "tf.Shape"(%432) {device = ""} : (tensor<?x?xi64>) -> tensor<2xi32>

	SYS_OPENDIR                         = 0x1AD // 429
	SYS_PATHCONF                        = 0x1AE // 430
	SYS_PAUSE                           = 0x1AF // 431
	SYS_PIPE                            = 0x1B0 // 432
	SYS_W_GETPSENT                      = 0x1B1 // 433
	SYS_READ                            = 0x1B2 // 434
	SYS_READDIR                         = 0x1B3 // 435
	SYS_READLINK                        = 0x1B4 // 436

// For DCBT Ra,Rb,TH, A value of TH indicates:
//     0, hint this cache line will be used soon. (PrefetchCache)
//     16, hint this cache line will not be used for long. (PrefetchCacheStreamed)
// See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/
(PrefetchCache ptr mem)          => (DCBT ptr mem [0])
(PrefetchCacheStreamed ptr mem)  => (DCBT ptr mem [16])

// Use byte reverse instructions on Power10

  %3 = "tf.Const"() {value = dense<4096> : tensor<i32>} : () -> tensor<i32>
  %4 = "tf.Const"() {value = dense<0> : tensor<i32>} : () -> tensor<i32>
  %5 = "tf.Range"(%4, %3, %2) : (tensor<i32>, tensor<i32>, tensor<i32>) -> tensor<4096xi32>
  %6 = "tf.Equal"(%1, %5) : (tensor<*xi32>, tensor<4096xi32>) -> tensor<*xi1>
  %7 = "tf.Cast"(%6) : (tensor<*xi1>) -> tensor<*xf32>