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Results 21 - 30 of 41 for fsub (0.11 sec)
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src/image/png/writer.go
// This is the same heuristic that libpng uses, although the filters are attempted in order of // estimated most likely to be minimal (ftUp, ftPaeth, ftNone, ftSub, ftAverage), rather than // in their enumeration order (ftNone, ftSub, ftUp, ftAverage, ftPaeth). cdat0 := cr[0][1:] cdat1 := cr[1][1:] cdat2 := cr[2][1:] cdat3 := cr[3][1:] cdat4 := cr[4][1:] pdat := pr[1:] n := len(cdat0)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 11 17:08:05 UTC 2024 - 15.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/a.out.go
ANEGV ANOOP // hardware nop ANOR AOR AREM AREMU ARFE ASC ASCV ASGT ASGTU ASLL ASQRTD ASQRTF ASRA ASRL AROTR ASUB ASUBD ASUBF ASUBU ASUBW ADBAR ASYSCALL ATEQ ATNE AWORD AXOR AMASKEQZ AMASKNEZ // 64-bit AMOVV AMOVVL AMOVVR
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/asmz.go
{i: 22, as: AADD, a1: C_LCON, a6: C_REG}, {i: 12, as: AADD, a1: C_LOREG, a6: C_REG}, {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG}, {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG}, {i: 21, as: ASUB, a1: C_LCON, a6: C_REG}, {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG}, {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG}, {i: 4, as: AMULHD, a1: C_REG, a6: C_REG}, {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 176.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/cpu.go
ASLTI ASLTIU AANDI AORI AXORI ASLLI ASRLI ASRAI ALUI AAUIPC AADD ASLT ASLTU AAND AOR AXOR ASLL ASRL ASUB ASRA // 2.5: Control Transfer Instructions AJAL AJALR ABEQ ABNE ABLT ABLTU ABGE ABGEU // 2.6: Load and Store Instructions ALW ALWU ALH ALHU
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
return true } return false } func rewriteValuePPC64_OpPPC64FSUB(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FSUB (FMUL x y) z) // cond: x.Block.Func.useFMA(v) // result: (FMSUB x y z) for { if v_0.Op != OpPPC64FMUL { break } _ = v_0.Args[1] v_0_0 := v_0.Args[0] v_0_1 := v_0.Args[1]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/internal/obj/mips/asm0.go
{AMOVWU, C_REG, C_NONE, C_REG, 14, 8, 0, sys.MIPS64, NOTUSETMP}, {ASUB, C_REG, C_REG, C_REG, 2, 4, 0, 0, 0}, {ASUBV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64, 0}, {AADD, C_REG, C_REG, C_REG, 2, 4, 0, 0, 0}, {AADDV, C_REG, C_REG, C_REG, 2, 4, 0, sys.MIPS64, 0}, {AAND, C_REG, C_REG, C_REG, 2, 4, 0, 0, 0}, {ASUB, C_REG, C_NONE, C_REG, 2, 4, 0, 0, 0}, {ASUBV, C_REG, C_NONE, C_REG, 2, 4, 0, sys.MIPS64, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 53.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FSUB", argLen: 2, asm: ppc64.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
SRL X6, X5, X7 // b3d36200 SRL X5, X6 // 33535300 SRL $1, X5, X6 // 13d31200 SRL $1, X5 // 93d21200 SUB X6, X5, X7 // b3836240 SUB X5, X6 // 33035340 SUB $-2047, X5, X6 // 1383f27f SUB $2048, X5, X6 // 13830280 SUB $-2047, X5 // 9382f27f SUB $2048, X5 // 93820280 SRA X6, X5, X7 // b3d36240 SRA X5, X6 // 33535340 SRA $1, X5, X6 // 13d31240
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x33, 0x5, 0x0, 0, 0x0} case ASRLI: return &inst{0x13, 0x5, 0x0, 0, 0x0} case ASRLIW: return &inst{0x1b, 0x5, 0x0, 0, 0x0} case ASRLW: return &inst{0x3b, 0x5, 0x0, 0, 0x0} case ASUB: return &inst{0x33, 0x0, 0x0, 1024, 0x20} case ASUBW: return &inst{0x3b, 0x0, 0x0, 1024, 0x20} case ASW: return &inst{0x23, 0x2, 0x0, 0, 0x0} case AWFI: return &inst{0x73, 0x0, 0x5, 261, 0x8}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/obj9.go
p.From.Offset = 0 } } } switch p.As { // Rewrite SUB constants into ADD. case ASUBC: if p.From.Type == obj.TYPE_CONST { p.From.Offset = -p.From.Offset p.As = AADDC } case ASUBCCC: if p.From.Type == obj.TYPE_CONST { p.From.Offset = -p.From.Offset p.As = AADDCCC } case ASUB: if p.From.Type != obj.TYPE_CONST { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 40.8K bytes - Viewed (0)