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Results 1 - 3 of 3 for STLXR (1.04 sec)
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src/internal/runtime/atomic/atomic_arm64.s
MOVBU internal∕cpu·ARM64+const_offsetARM64HasATOMICS(SB), R4 CBZ R4, load_store_loop #endif SWPALD R1, (R0), R2 MOVD R2, ret+16(FP) RET #ifndef GOARM64_LSE load_store_loop: LDAXR (R0), R2 STLXR R1, (R0), R3 CBNZ R3, load_store_loop MOVD R2, ret+16(FP) RET #endif // bool Cas(uint32 *ptr, uint32 old, uint32 new) // Atomically: // if(*val == old){ // *val = new; // return 1;
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
// atomic exchange. // store arg1 to arg0. arg2=mem. returns <old content of *arg0, memory>. auxint must be zero. // LDAXR (Rarg0), Rout // STLXR Rarg1, (Rarg0), Rtmp // CBNZ Rtmp, -2(PC) {name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
c.ctxt.Diag("constrained unpredictable behavior: %v", p) } o1 |= uint32(p.To.Offset&31) << 10 } else { o1 |= 0x1F << 10 } o1 |= uint32(p.To.Reg & 31) case 59: /* stxr/stlxr/stxp/stlxp */ s := p.RegTo2 n := p.To.Reg t := p.From.Reg if isSTLXRop(p.As) { if s == t || (s == n && n != REGSP) { c.ctxt.Diag("constrained unpredictable behavior: %v", p) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0)