MOVBU	internal∕cpu·ARM64+const_offsetARM64HasATOMICS(SB), R4
	CBZ 	R4, load_store_loop
#endif
	SWPALD	R1, (R0), R2
	MOVD	R2, ret+16(FP)
	RET
#ifndef GOARM64_LSE
load_store_loop:
	LDAXR	(R0), R2
	STLXR	R1, (R0), R3
	CBNZ	R3, load_store_loop
	MOVD	R2, ret+16(FP)
	RET
#endif

// bool Cas(uint32 *ptr, uint32 old, uint32 new)
// Atomically:
//	if(*val == old){
//		*val = new;
//		return 1;

	FCSELD EQ, F15, F18, F16    <=>    fcsel d16, d15, d18, eq

(10) TBNZ, TBZ $<imm>, <Rt>, <label>

(11) STLXR, STLXRW, STXR, STXRW, STLXRB, STLXRH, STXRB, STXRH  <Rf>, (<Rn|RSP>), <Rs>

Examples:

	STLXR ZR, (R15), R16    <=>    stlxr w16, xzr, [x15]
	STXRB R9, (R21), R19    <=>    stxrb w19, w9, [x21]

(12) STLXP, STLXPW, STXP, STXPW (<Rf1>, <Rf2>), (<Rn|RSP>), <Rs>

Examples:

	"SHA512H2",
	"SHA512SU0",
	"SHA512SU1",
	"SMADDL",
	"SMC",
	"SMNEGL",
	"SMSUBL",
	"SMULH",
	"SMULL",
	"STLR",
	"STLRB",
	"STLRH",
	"STLRW",
	"STLXP",
	"STLXPW",
	"STLXR",
	"STLXRB",
	"STLXRH",
	"STLXRW",
	"STP",
	"STPW",
	"STXP",
	"STXPW",
	"STXR",
	"STXRB",
	"STXRH",
	"STXRW",
	"SUB",
	"SUBS",
	"SUBSW",
	"SUBW",
	"SVC",

		arm64.AFCMPS, arm64.AFCMPD,
		arm64.AFCMPES, arm64.AFCMPED:
		return true
	}
	return false
}

// IsARM64STLXR reports whether the op (as defined by an arm64.A*
// constant) is one of the STLXR-like instructions that require special
// handling.
func IsARM64STLXR(op obj.As) bool {
	switch op {
	case arm64.ASTLXRB, arm64.ASTLXRH, arm64.ASTLXRW, arm64.ASTLXR,

	STLXP	(R6, R11), (RSP), R6                             // ERROR "constrained unpredictable behavior"
	STXP	(R6, R11), (R2), R2                              // ERROR "constrained unpredictable behavior"
	STLXR	R3, (RSP), R3                                    // ERROR "constrained unpredictable behavior"
	STXR	R3, (R4), R4                                     // ERROR "constrained unpredictable behavior"

		// atomic exchange.
		// store arg1 to arg0. arg2=mem. returns <old content of *arg0, memory>. auxint must be zero.
		// LDAXR	(Rarg0), Rout
		// STLXR	Rarg1, (Rarg0), Rtmp
		// CBNZ		Rtmp, -2(PC)
		{name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},

	// STLXP <Ws>, <Xt>, <Xt2>, [<Xn|SP>{, #0}]
	{0xffe08000, 0xc8208000, STLXP, instArgs{arg_Ws, arg_Xt, arg_Xt2, arg_Xns_mem}, nil},
	// STLXR <Ws>, <Wt>, [<Xn|SP>{, #0}]
	{0xffe08000, 0x88008000, STLXR, instArgs{arg_Ws, arg_Wt, arg_Xns_mem}, nil},
	// STLXR <Ws>, <Xt>, [<Xn|SP>{, #0}]
	{0xffe08000, 0xc8008000, STLXR, instArgs{arg_Ws, arg_Xt, arg_Xns_mem}, nil},
	// STLXRB <Ws>, <Wt>, [<Xn|SP>{, #0}]

			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[0], args[1] = args[1], args[0]

	case STLRB, STLRH:
		args[0], args[1] = args[1], args[0]

	case STLXR, STXR:
		if r, ok := inst.Args[1].(Reg); ok {
			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[1], args[2] = args[2], args[1]

	case STLXRB, STLXRH, STXRB, STXRH:

	STLRW R16, (R22)                           // d0fe9f88
	STLR R3, (R24)                             // 03ff9fc8
	STLRB R11, (R22)                           // cbfe9f08
	STLRH R16, (R23)                           // f0fe9f48
	STLXR R7, (R27), R8                        // 67ff08c8
	STLXRW R13, (R15), R14                     // edfd0e88
	STLXRB R24, (R23), R8                      // f8fe0808
	STLXRH R19, (R27), R11                     // 73ff0b48

{"Name":"STLXR","Bits":"10:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLXR <Ws>, <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLXR","Bits":"11:2|0|0|1|0|0|0|0|0|0|Rs:5|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLXR <Ws>, <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},