"SHA256H",
	"SHA256H2",
	"SHA256SU0",
	"SHA256SU1",
	"SHA512H",
	"SHA512H2",
	"SHA512SU0",
	"SHA512SU1",
	"SMADDL",
	"SMC",
	"SMNEGL",
	"SMSUBL",
	"SMULH",
	"SMULL",
	"STLR",
	"STLRB",
	"STLRH",
	"STLRW",
	"STLXP",
	"STLXPW",
	"STLXR",
	"STLXRB",
	"STLXRH",
	"STLXRW",
	"STP",
	"STPW",
	"STXP",
	"STXPW",
	"STXR",
	"STXRB",
	"STXRH",

	RET

TEXT ·Store8(SB), NOSPLIT, $0-9
	MOVD	ptr+0(FP), R0
	MOVB	val+8(FP), R1
	STLRB	R1, (R0)
	RET

TEXT ·Store64(SB), NOSPLIT, $0-16
	MOVD	ptr+0(FP), R0
	MOVD	val+8(FP), R1
	STLR	R1, (R0)
	RET

// uint32 Xchg(ptr *uint32, new uint32)
// Atomically:
//	old := *ptr;
//	*ptr = new;
//	return old;
TEXT ·Xchg(SB), NOSPLIT, $0-20
	MOVD	ptr+0(FP), R0
	MOVW	new+8(FP), R1

	VADD V16, V19, V14             <=>      add d14, d19, d16

Special Cases.

(1) Argument order is the same as in the GNU ARM64 syntax: cbz, cbnz and some store instructions,
such as str, stur, strb, sturb, strh, sturh stlr, stlrb. stlrh, st1.

Examples:

	MOVD R29, 384(R19)    <=>    str x29, [x19,#384]
	MOVB.P R30, 30(R4)    <=>    strb w30, [x4],#30
	STLRH R21, (R19)      <=>    stlrh w21, [x19]

	// SMULH <Xd>, <Xn>, <Xm>
	{0xffe08000, 0x9b400000, SMULH, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
	// STLR <Wt>, [<Xn|SP>{, #0}]
	{0xffe08000, 0x88808000, STLR, instArgs{arg_Wt, arg_Xns_mem}, nil},
	// STLR <Xt>, [<Xn|SP>{, #0}]
	{0xffe08000, 0xc8808000, STLR, instArgs{arg_Xt, arg_Xns_mem}, nil},
	// STLRB <Wt>, [<Xn|SP>{, #0}]
	{0xffe08000, 0x08808000, STLRB, instArgs{arg_Wt, arg_Xns_mem}, nil},

	case MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL:
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[2], args[3] = args[3], args[2]
	case STLR:
		if r, ok := inst.Args[0].(Reg); ok {
			rno := uint16(r)
			if rno <= uint16(WZR) {
				op += "W"
			}
		}
		args[0], args[1] = args[1], args[0]

	case STLRB, STLRH:

		// atomic stores.
		// store arg1 to arg0. arg2=mem. returns memory. auxint must be zero.
		{name: "STLRB", argLength: 3, reg: gpstore, asm: "STLRB", faultOnNilArg0: true, hasSideEffects: true},
		{name: "STLR", argLength: 3, reg: gpstore, asm: "STLR", faultOnNilArg0: true, hasSideEffects: true},
		{name: "STLRW", argLength: 3, reg: gpstore, asm: "STLRW", faultOnNilArg0: true, hasSideEffects: true},

		// atomic exchange.

	SMULH R17, R21, R21                        // b57e519b
	SMULL R0, R5, R0                           // a07c209b
	SMC $37977                                 // 238b12d4
	STLRW R16, (R22)                           // d0fe9f88
	STLR R3, (R24)                             // 03ff9fc8
	STLRB R11, (R22)                           // cbfe9f08
	STLRH R16, (R23)                           // f0fe9f48
	STLXR R7, (R27), R8                        // 67ff08c8

{"Name":"STLR","Bits":"10:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STLR <Wt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},
{"Name":"STLR","Bits":"11:2|0|0|1|0|0|0|1|0|0|(1)|(1)|(1)|(1)|(1)|1|(1)|(1)|(1)|(1)|(1)|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STLR <Xt>, [<Xn|SP>{,#0}]","Code":"","Alias":""},

(AtomicLoad64  ...) => (LDAR  ...)
(AtomicLoadPtr ...) => (LDAR  ...)

(AtomicStore8       ...) => (STLRB ...)
(AtomicStore32      ...) => (STLRW ...)
(AtomicStore64      ...) => (STLR  ...)
(AtomicStorePtrNoWB ...) => (STLR  ...)

(AtomicExchange(32|64)       ...) => (LoweredAtomicExchange(32|64) ...)
(AtomicAdd(32|64)            ...) => (LoweredAtomicAdd(32|64)      ...)

				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "STLR",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            arm64.ASTLR,
		reg: regInfo{
			inputs: []inputInfo{