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Results 21 - 30 of 56 for add_args (0.26 sec)
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src/cmd/compile/internal/ssa/rewrite386splitload.go
sym := auxToSym(v.Aux) ptr := v_0 x := v_1 mem := v_2 v.reset(Op386CMPB) v0 := b.NewValue0(v.Pos, Op386MOVBload, typ.UInt8) v0.AuxInt = int32ToAuxInt(off) v0.Aux = symToAux(sym) v0.AddArg2(ptr, mem) v.AddArg2(v0, x) return true } } func rewriteValue386splitload_Op386CMPLconstload(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64latelower.go
for { x := v_0 if x.Op != OpARM64MOVBUload { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUloadidx _ _ _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVBUloadidx { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVBUreg x:(MOVBUreg _)) // result: (MOVDreg x) for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 19.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64latelower.go
v.AuxInt = int32ToAuxInt(a) v.AddArg2(x, z) return true } // match: (ISEL [a] (MOVDconst [0]) y z) // result: (ISELZ [a^0x4] y z) for { a := auxIntToInt32(v.AuxInt) if v_0.Op != OpPPC64MOVDconst || auxIntToInt64(v_0.AuxInt) != 0 { break } y := v_1 z := v_2 v.reset(OpPPC64ISELZ) v.AuxInt = int32ToAuxInt(a ^ 0x4) v.AddArg2(y, z) return true } return false
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 16.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/trim.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 18 17:59:44 UTC 2022 - 4.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/decompose.go
cap := v.Block.NewValue0(v.Pos, OpPhi, lenType) for _, a := range v.Args { ptr.AddArg(a.Block.NewValue1(v.Pos, OpSlicePtr, ptrType, a)) len.AddArg(a.Block.NewValue1(v.Pos, OpSliceLen, lenType, a)) cap.AddArg(a.Block.NewValue1(v.Pos, OpSliceCap, lenType, a)) } v.reset(OpSliceMake) v.AddArg(ptr) v.AddArg(len) v.AddArg(cap) } func decomposeInt64Phi(v *Value) { cfgtypes := &v.Block.Func.Config.Types
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 23 21:22:15 UTC 2022 - 13.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/expand_calls.go
mem = x.decomposeAsNecessary(v.Pos, v.Block, a, mem, rc) } var preArgStore [2]*Value preArgs := append(preArgStore[:0], v.Args[0:firstArg]...) v.resetArgs() v.AddArgs(preArgs...) v.AddArgs(allResults...) v.AddArg(mem) for _, a := range oldArgs { if a.Uses == 0 { x.invalidateRecursively(a) } } return }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 28 05:13:40 UTC 2023 - 31.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/passes/prepare_lifting.td
$_ ), (TF_ConstOp:$add_rhs IsFloatElementsAttr:$add_rhs_value)), (TF_BiasAddOp $reshape_out, $add_rhs, (CreateStringAttr<"NHWC">)), [(HasRankOf<1> $add_rhs_value), (HasEqualElementSize<[-1], [0]> $reshape_out, $add_rhs)]>; // Fuse consecutive BiasAddOp and an AddV2Op. // We also handle the case where add_rhs has rank 4. def FuseBiasAndAddV2 : Pat< (TF_AddV2Op
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Feb 14 03:24:59 UTC 2024 - 8.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64latelower.go
v.reset(OpAMD64SHLXL) v.AddArg2(x, y) return true } return false } func rewriteValueAMD64latelower_OpAMD64SHLQ(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (SHLQ x y) // cond: buildcfg.GOAMD64 >= 3 // result: (SHLXQ x y) for { x := v_0 y := v_1 if !(buildcfg.GOAMD64 >= 3) { break } v.reset(OpAMD64SHLXQ) v.AddArg2(x, y) return true }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 3.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64latelower.go
x := v_0.Args[0] if !(c <= 56) { break } v.reset(OpRISCV64SRLI) v.AuxInt = int64ToAuxInt(56 - c) v0 := b.NewValue0(v.Pos, OpRISCV64SLLI, typ.UInt64) v0.AuxInt = int64ToAuxInt(56) v0.AddArg(x) v.AddArg(v0) return true } // match: (SLLI [c] (MOVHUreg x)) // cond: c <= 48 // result: (SRLI [48-c] (SLLI <typ.UInt64> [48] x)) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVHUreg {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 5.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/softfloat.go
v.Type = f.Config.Types.UInt32 v.AddArg(arg0) mask := v.Block.NewValue0(v.Pos, OpConst32, v.Type) mask.AuxInt = -0x80000000 v.AddArg(mask) case OpNeg64F: arg0 := v.Args[0] v.reset(OpXor64) v.Type = f.Config.Types.UInt64 v.AddArg(arg0) mask := v.Block.NewValue0(v.Pos, OpConst64, v.Type) mask.AuxInt = -0x8000000000000000 v.AddArg(mask) case OpRound32F:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 03 16:14:24 UTC 2021 - 2K bytes - Viewed (0)