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Results 1 - 10 of 57 for add_args (0.15 sec)

  1. tensorflow/compiler/mlir/tf2xla/internal/utils/test_metadata_config.cc

            xla_shape.dimensions(), &tensor_shape));
        arg_shapes.emplace_back(tensor_shape);
    
        DataType dtype;
        TF_RETURN_IF_ERROR(ConvertToDataType(input_type, &dtype));
    
        auto metadata_arg = metadata_proto.add_args();
        metadata_arg->set_kind(tpu::TPUCompileMetadataProto::Arg::PARAMETER);
        metadata_arg->set_dtype(dtype);
      }
    
      return absl::OkStatus();
    }
    
    absl::Status SetupReturnValues(mlir::ModuleOp module,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 13 23:59:33 UTC 2024
    - 3.9K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tf2xla/internal/legalize_tf_to_hlo_test.cc

      auto client =
          xla::ClientLibrary::GetOrCreateCompileOnlyClient(platform).value();
    
      std::vector<TensorShape> arg_shapes = {{1}};
      TPUCompileMetadataProto metadata_proto;
      auto arg = metadata_proto.add_args();
      arg->set_dtype(DataType::DT_FLOAT);
      arg->set_kind(TPUCompileMetadataProto::Arg::PARAMETER);
      metadata_proto.add_retvals();
      bool use_tuple_args = true;
      std::vector<ShardingAndIndex> arg_core_mapping;
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sun Apr 14 20:29:34 UTC 2024
    - 6K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/quantization/stablehlo/passes/bridge/legalize_tf_quant_test.cc

        tensorflow::tpu::TPUCompileMetadataProto metadata_proto;
        // Set up an arg per arg_shape with the specified type.
        for (int i = 0; i < arg_shapes.size(); ++i) {
          auto metadata_arg = metadata_proto.add_args();
          metadata_arg->set_kind(
              tensorflow::tpu::TPUCompileMetadataProto::Arg::PARAMETER);
          metadata_arg->set_dtype(dtype);
        }
        // Set up one dummy retval.
        metadata_proto.add_retvals();
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Feb 29 18:43:55 UTC 2024
    - 7.2K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/transforms/host_runtime/tpu_metadata_utils.cc

        Type operand_type = operand_type_and_idx.value();
        int index = operand_type_and_idx.index();
        tensorflow::tpu::TPUCompileMetadataProto::Arg* arg = metadata->add_args();
        tensorflow::DataType dtype;
        tensorflow::Status status =
            tensorflow::ConvertToDataType(operand_type, &dtype);
        if (!status.ok())
          return op.emitOpError(
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 10.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteMIPS.go

    		v6.AuxInt = int32ToAuxInt(3)
    		v6.AddArg(ptr)
    		v5.AddArg(v6)
    		v3.AddArg2(v4, v5)
    		v7 := b.NewValue0(v.Pos, OpMIPSNORconst, typ.UInt32)
    		v7.AuxInt = int32ToAuxInt(0)
    		v8 := b.NewValue0(v.Pos, OpMIPSSLL, typ.UInt32)
    		v9 := b.NewValue0(v.Pos, OpMIPSMOVWconst, typ.UInt32)
    		v9.AuxInt = int32ToAuxInt(0xff)
    		v8.AddArg2(v9, v5)
    		v7.AddArg(v8)
    		v2.AddArg2(v3, v7)
    		v.AddArg3(v0, v2, mem)
    		return true
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 176.6K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/rewritedec.go

    		v4.AuxInt = int64ToAuxInt(t.FieldOff(1))
    		v4.AddArg(dst)
    		v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
    		v5.Aux = typeToAux(t.FieldType(0))
    		v6 := b.NewValue0(v.Pos, OpOffPtr, t.FieldType(0).PtrTo())
    		v6.AuxInt = int64ToAuxInt(0)
    		v6.AddArg(dst)
    		v5.AddArg3(v6, f0, mem)
    		v3.AddArg3(v4, f1, v5)
    		v1.AddArg3(v2, f2, v3)
    		v.AddArg3(v0, f3, v1)
    		return true
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 00:48:31 UTC 2023
    - 24.9K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/rewriteARM64.go

    		v0.AuxInt = int64ToAuxInt(c)
    		v0.AddArg(x)
    		v.AddArg(v0)
    		return true
    	}
    	// match: (CMP x y)
    	// cond: canonLessThan(x,y)
    	// result: (InvertFlags (CMP y x))
    	for {
    		x := v_0
    		y := v_1
    		if !(canonLessThan(x, y)) {
    			break
    		}
    		v.reset(OpARM64InvertFlags)
    		v0 := b.NewValue0(v.Pos, OpARM64CMP, types.TypeFlags)
    		v0.AddArg2(y, x)
    		v.AddArg(v0)
    		return true
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 608.6K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/rewritePPC64.go

    		v2.AuxInt = int64ToAuxInt(-1)
    		v2.AddArg(x)
    		v1.AddArg2(v2, x)
    		v0.AddArg(v1)
    		v.AddArg(v0)
    		return true
    	}
    	// match: (Ctz32 x)
    	// result: (CNTTZW (MOVWZreg x))
    	for {
    		x := v_0
    		v.reset(OpPPC64CNTTZW)
    		v0 := b.NewValue0(v.Pos, OpPPC64MOVWZreg, typ.Int64)
    		v0.AddArg(x)
    		v.AddArg(v0)
    		return true
    	}
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 360.2K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteS390X.go

    		v3 := b.NewValue0(v.Pos, OpS390XANDW, t)
    		v4 := b.NewValue0(v.Pos, OpS390XSUBWconst, t)
    		v4.AuxInt = int32ToAuxInt(1)
    		v4.AddArg(x)
    		v5 := b.NewValue0(v.Pos, OpS390XNOTW, t)
    		v5.AddArg(x)
    		v3.AddArg2(v4, v5)
    		v2.AddArg(v3)
    		v1.AddArg(v2)
    		v.AddArg2(v0, v1)
    		return true
    	}
    }
    func rewriteValueS390X_OpCtz64(v *Value) bool {
    	v_0 := v.Args[0]
    	b := v.Block
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 395.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    		v4.AuxInt = int32ToAuxInt(1)
    		v4.AddArg2(src, mem)
    		v5 := b.NewValue0(v.Pos, OpRISCV64MOVBstore, types.TypeMem)
    		v6 := b.NewValue0(v.Pos, OpRISCV64MOVBload, typ.Int8)
    		v6.AddArg2(src, mem)
    		v5.AddArg3(dst, v6, mem)
    		v3.AddArg3(dst, v4, v5)
    		v1.AddArg3(dst, v2, v3)
    		v.AddArg3(dst, v0, v1)
    		return true
    	}
    	// match: (Move [8] {t} dst src mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
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