Search Options

Results per page
Sort
Preferred Languages
Advance

Results 21 - 30 of 667 for arg0 (0.05 sec)

  1. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_composite_functions.mlir

    // CHECK-LABEL: func private @quantized_conv2d_with_bias_and_relu6_fn_0
    // CHECK-SAME: (%arg0: tensor<1x2x2x3xi8>, %arg1: tensor<2x2x3x2xi8>, %arg2: tensor<2xi32>, %arg3: tensor<f32>, %arg4: tensor<i32>, %arg5: tensor<2xf32>, %arg6: tensor<2xi32>, %arg7: tensor<2xf32>, %arg8: tensor<2xi32>, %arg9: tensor<f32>, %arg10: tensor<i32>) -> tensor<*xi8>
    // CHECK:      %[[CONV2D_0:.*]] = "tf.Conv2D"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Nov 06 01:23:21 UTC 2023
    - 15.2K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir

    func.func @argmin(%arg0: tensor<3xi32>, %arg1: tensor<i32>) -> tensor<i32> {
      %0 = "tf.ArgMin"(%arg0, %arg1) : (tensor<3xi32>, tensor<i32>) -> tensor<i32>
      func.return %0 : tensor<i32>
    
    // CHECK-LABEL: argmin
    // CHECK:  "tfl.arg_min"(%arg0, %arg1) : (tensor<3xi32>, tensor<i32>) -> tensor<i32>
    }
    
    func.func @sigmoid(%arg0: tensor<?x88xf32>) -> tensor<?x88xf32> {
      %0 = "tf.Sigmoid"(%arg0) : (tensor<?x88xf32>) -> tensor<?x88xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 05 01:54:33 UTC 2024
    - 153.4K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/tensorflow/tests/canonicalize.mlir

      %1 = "tf.Concat"(%0, %arg0, %arg1) {device = "/job:localhost/replica:0/task:0/device:GPU:0"} : (tensor<i32>, tensor<2x1xi32>, tensor<2x1xi32>) -> tensor<2x2xi32>
      func.return %1 : tensor<2x2xi32>
    }
    
    // CHECK-LABEL: testConcatCwiseUnary
    func.func @testConcatCwiseUnary(%arg0: tensor<?x1xf32>, %arg1: tensor<?x1xf32>, %arg2: tensor<i32>) -> tensor<?x2xf32> {
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 09 22:07:10 UTC 2024
    - 132.1K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/quantization/tensorflow/tests/replace_cast_hacks_with_tf_xla_ops_large_constants.mlir

        %cst = "tf.Const"() {value = dense<127> : tensor<i32>} : () -> tensor<i32>
        %cst_0 = "tf.Const"() {value = dense<-128> : tensor<i32>} : () -> tensor<i32>
        %0 = "tf.Cast"(%arg0) {Truncate = false} : (tensor<1x2240x2240x3xi8>) -> tensor<1x2240x2240x3xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 5.9K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/lite/stablehlo/tests/legalize-stablehlo-vhlo.mlir

    func.func @op_with_region_mixed_tfl_shlo_tfl(%arg0: tensor<7x5xf32>, %arg1 : tensor<5xf32>) -> tensor<5xf32> {
      %0 = "stablehlo.reduce"(%arg0, %arg1) ({
      ^bb0(%arg2: tensor<5xf32>, %arg3: tensor<5xf32>):
        // CHECK:      %1 = "tfl.abs"(%arg2) {fused_activation_function = "NONE"} : (tensor<5xf32>) -> tensor<5xf32>
        // CHECK-NEXT: %2 = "vhlo.add_v1"(%1, %arg2) : (tensor<5xf32>, tensor<5xf32>) -> tensor<5xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Mar 07 22:39:35 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/tests/prepare-tf.mlir

    // CHECK-LABEL: identity
    // CHECK: %0 = "tf.Identity"(%arg0) : (tensor<10xi32>) -> tensor<*xi32>
    // CHECK: return %arg0, %arg1, %arg2, %0
    }
    
    func.func @sharding(%arg0: tensor<10x10xi32>) -> (tensor<10x10xi32>) {
      %0 = "tf.MatMul"(%arg0, %arg0) {device = "", transpose_a = false, transpose_b = false} : (tensor<10x10xi32>, tensor<10x10xi32>) -> tensor<10x10xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 29 07:26:59 UTC 2024
    - 59.8K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/tensorflow/tests/region-control-flow-to-functional.mlir

    // CHECK: func private @tf.IfRegion_else(%arg0: tensor<i1>, %arg1: tensor<2xf32>, %arg2: tensor<2xf32>, %arg3: tensor<2xf32>) -> tensor<2xf32>
    // CHECK-NEXT: "tf.Select"(%arg0, %arg2, %arg3)
    // CHECK: func private @tf.IfRegion_then(%arg0: tensor<i1>, %arg1: tensor<2xf32>, %arg2: tensor<2xf32>, %arg3: tensor<2xf32>) -> tensor<2xf32>
    // CHECK-NEXT: "tf.Select"(%arg0, %arg1, %arg2)
    func.func @testIfCondition(%arg0: tensor<i1>, %arg1: tensor<2xf32>) -> tensor<2xf32> {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Feb 02 11:15:34 UTC 2024
    - 44.3K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tensorflow/tests/tpu_sharding_identification.mlir

    func.func @func_with_sharding_inside_while_body(%arg0: tensor<i32>, %arg1: tensor<128x1024xf32>) -> (tensor<128x1024xf32>) {
      %cst = "tf.Const"() <{value = dense<0> : tensor<i32>}> {device = ""} : () -> tensor<i32>
      %0:2 = "tf.WhileRegion"(%cst, %arg1) <{is_stateless = false, parallel_iterations = 1 : i64}> ({
        ^bb0(%arg2: tensor<i32>, %arg3: tensor<128x1024xf32>):
          %1 = "tf.Less"(%arg2, %arg0) : (tensor<i32>, tensor<i32>) -> tensor<i1>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Feb 20 19:07:52 UTC 2024
    - 47.5K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tensorflow/tests/convert_control_to_data_outputs.mlir

    func.func @unknown_resource_op_while_body(%arg0: !tf_res, %arg1: !tf_res, %arg2: tensor<f32>, %arg3: tensor<f32>) -> (!tf_res, !tf_res, tensor<f32>, tensor<f32>) {
      %graph:4 = tf_executor.graph {
        %assign_control_0 = tf_executor.island wraps "tf.AssignVariableOp"(%arg0, %arg2) : (tensor<!tf_type.resource<tensor<f32>>>, tensor<f32>) -> ()
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Feb 22 18:35:00 UTC 2024
    - 68.9K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2)
    		{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2)
    		{name: "MADD", argLength: 3, reg: gp31, asm: "MADD"},       // +arg0 + (arg1 * arg2)
    		{name: "MADDW", argLength: 3, reg: gp31, asm: "MADDW"},     // +arg0 + (arg1 * arg2), 32-bit
    		{name: "MSUB", argLength: 3, reg: gp31, asm: "MSUB"},       // +arg0 - (arg1 * arg2)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
Back to top