{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops.
		{name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"},                      // arg0 - arg1
		{name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"},   // arg0 - auxInt

	ADDV	R25, R2
	// Is the buffer full?
	SGTU	R2, R23, R23
	BNE	R23, flush
	// Commit to the larger buffer.
	MOVV	R2, (p_wbBuf+wbBuf_next)(R1)
	// Make return value (the original next position)
	SUBV	R25, R2, R25
	// Restore registers.
	MOVV	184(R29), R1
	MOVV	192(R29), R2
	RET

flush:
	// Save all general purpose registers since these could be

	ADDV	R29, R13
	// Is the buffer full?
	BLTU	R30, R13, flush
	// Commit to the larger buffer.
	MOVV	R13, (p_wbBuf+wbBuf_next)(R19)
	// Make return value (the original next position)
	SUBV	R29, R13, R29
	// Restore registers.
	MOVV	208(R3), R19
	MOVV	216(R3), R13
	RET

flush:
	// Save all general purpose registers since these could be

	SUBCCC R3, R4, R5               // 7ca32011
	SUBCV R3, R4, R5                // 7ca32410
	SUBCVCC R3, R4, R5              // 7ca32411
	SUBMEVCC R3, R4                 // 7c8305d1
	SUBV R3, R4, R5                 // 7ca32450
	SUBE R3, R4, R5                 // 7ca32110
	SUBECC R3, R4, R5               // 7ca32111
	SUBEV R3, R4, R5                // 7ca32510
	SUBEVCC R3, R4, R5              // 7ca32511

			},
			outputs: []outputInfo{
				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:   "SUBV",
		argLen: 2,
		asm:    loong64.ASUBVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31