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Results 61 - 70 of 184 for stride_w (0.18 sec)

  1. tensorflow/compiler/mlir/lite/stablehlo/transforms/legalize_hlo.cc

          return failure();
        }
    
        // Constructs strides array.
        // For example, [2, 3] -> [1, 2, 3, 1].
        SmallVector<int64_t, num_spatial_dims + 2> strides({1});
        for (const auto v :
             conv_op.getWindowStrides().value().getValues<int64_t>()) {
          strides.emplace_back(v);
        }
        strides.emplace_back(1);
    
        // Constructs dilation array.
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 154.9K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/quantization/tensorflow/passes/lift_quantizable_spots_as_functions.td

    def LiftConv : Pat<
      (TF_Conv2DOp:$res $input, $filter, $strides, $use_cudnn_on_gpu, $padding,
        $explicit_paddings, IsDataFormatNHWC:$data_format, $dilations),
      (LiftAsTFPartitionedCall<"composite_conv2d_fn">
        (ArgumentList $input, $filter),
        (ResultList $res),
        (NamedAttributeList
          (NamedAttr<"strides"> $strides),
          (NamedAttr<"use_cudnn_on_gpu"> $use_cudnn_on_gpu),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sun Dec 10 05:52:02 UTC 2023
    - 15.6K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/quantization/tensorflow/passes/lift_quantizable_spots_as_functions_drq.td

    def LiftConv : Pat<
      (TF_Conv2DOp:$res $input, $filter, $strides, $use_cudnn_on_gpu, $padding,
        $explicit_paddings, IsDataFormatNHWC:$data_format, $dilations),
      (LiftAsTFPartitionedCall<"composite_conv2d_fn">
        (ArgumentList $input, $filter),
        (ResultList $res),
        (NamedAttributeList
          (NamedAttr<"strides"> $strides),
          (NamedAttr<"use_cudnn_on_gpu"> $use_cudnn_on_gpu),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sun Dec 10 05:52:02 UTC 2023
    - 3.9K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/fused_kernel_matcher.mlir

      // CHECK: %[[VAL_1:.*]] = "tf.Identity"(%[[VAL_0]]) : (tensor<*xf32>) -> tensor<*xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 13.2K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/quantization/tensorflow/passes/replace_cast_hacks_with_tf_xla_ops.td

      (TF_Conv2DOp:$conv
        (TF_SubOp (TF_CastOp $input, $truncate), $input_zp),
        (TF_CastOp (TF_IdentityOp $filter), $truncate1),
        $strides, $use_cudnn, $padding, $explicit_padding,
        IsDataFormatNHWC:$data_format, $dilations),
      (CreateXLAConvOpFromTFConv2DOp
        $input, $filter, $input_zp, $conv, $strides,
        $dilations, $padding, $explicit_padding),
      [(IsInt8ElementType $input),
       (IsInt8ElementType $filter),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sun Dec 10 05:52:02 UTC 2023
    - 21.1K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/quantization/tensorflow/tests/fallback_to_flex_ops_default.mlir

    func.func @conv2d_backprop_input_with_add(%arg0: tensor<4xi32>, %arg1: tensor<3x3x1x32xf32>, %arg2: tensor<15x14x14x32xf32>) -> tensor<15x28x28x1xf32> {
      %0 = "tf.Conv2DBackpropInput"(%arg0, %arg1, %arg2) {strides = [1, 2, 2, 1], padding="SAME", dilations=[1, 1, 1, 1]}: (tensor<4xi32>, tensor<3x3x1x32xf32>, tensor<15x14x14x32xf32>) -> tensor<15x28x28x1xf32>
      %1 = "tf.Const"() {value = dense<1.000000e+00> : tensor<1xf32>} : () -> tensor<1xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 13.4K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/quantization/tensorflow/tests/lift_quantizable_spots_as_functions.mlir

    // CHECK-NEXT: %[[CONV2D_0:.*]] = "tf.Conv2D"(%arg0, %arg1)
    // CHECK-SAME: data_format = "NHWC", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true
    // CHECK-SAME: attr_map = "0:strides,1:use_cudnn_on_gpu,2:padding,3:explicit_paddings,4:dilations"
    // CHECK-NEXT: %[[BIASADD_0:.*]] = "tf.BiasAdd"(%[[CONV2D_0]], %arg2)
    // CHECK-NEXT: %[[RELU6_0:.*]] = "tf.Relu6"(%[[BIASADD_0]])
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri May 10 04:07:09 UTC 2024
    - 26.5K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_composite_functions.mlir

        %0 = "tf.Conv2D"(%arg0, %arg1) {attr_map = "0:strides,1:use_cudnn_on_gpu,2:padding,3:explicit_paddings,4:dilations", data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "VALID", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true} : (tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Nov 06 01:23:21 UTC 2023
    - 15.2K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/quantization/tensorflow/tests/lift_quantizable_spots_as_functions_drq.mlir

    // CHECK-SAME: attr_map = "0:strides,1:use_cudnn_on_gpu,2:padding,3:explicit_paddings,4:dilations"
    // CHECK-NEXT: return %[[CONV2D_0]]
    
    // CHECK-LABEL: private @composite_conv2d_fn_1
    // CHECK-NEXT: %[[CONV2D_0:.*]] = "tf.Conv2D"(%arg0, %arg1)
    // CHECK-SAME: attr_map = "0:strides,1:use_cudnn_on_gpu,2:padding,3:explicit_paddings,4:dilations"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 11.8K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/quantization/tensorflow/tests/preprocess_op_weight_only.mlir

        %0 = "tf.DepthwiseConv2dNative"(%arg0, %arg1) {
          attr_map = "0:strides,1:padding,2:explicit_paddings,3:dilations", data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1]
        } : (tensor<1x3x4x3xf32>, tensor<2x3x3x2xf32>) -> tensor<*xf32>
        return %0 : tensor<*xf32>
      }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.7K bytes
    - Viewed (0)
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