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Results 1 - 10 of 232 for stride_w (0.11 sec)

  1. tensorflow/compiler/mlir/tfr/examples/mnist/ops_defs.py

          input=input_, ksize=ksize, strides=strides, padding=padding)
    
    
    @tf.RegisterGradient('NewMaxPool')
    def _max_pool_grad(op: ops.Operation, grad):
      filter_width = op.get_attr('filter_width')
      filter_height = op.get_attr('filter_height')
      stride_w = op.get_attr('stride_w')
      stride_h = op.get_attr('stride_h')
      padding = op.get_attr('padding')
      return tf.raw_ops.MaxPoolGrad(
          orig_input=op.inputs[0],
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Aug 31 20:23:51 UTC 2023
    - 6.8K bytes
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  2. tensorflow/compiler/mlir/lite/tests/decompose-hybrid-quantization.mlir

      // CHECK: %[[VAL3:.+]] = "tfl.conv_3d"(%arg0, %[[VAL2]], %[[VAL0]]) <{dilation_d_factor = 1 : i32, dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, fused_activation_function = "NONE", padding = "SAME", stride_d = 1 : i32, stride_h = 1 : i32, stride_w = 1 : i32}>
      // CHECK: return %[[VAL3]]
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 13.1K bytes
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  3. tensorflow/compiler/mlir/lite/tests/shape-inference.mlir

      %0 = "tfl.conv_2d"(%arg0, %arg1, %arg2) {dilation_h_factor = 2 : i32, dilation_w_factor = 2 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 1 : i32, stride_w = 1 : i32} : (tensor<1x112x80x128xf32>, tensor<128x3x3x128xf32>, tensor<128xf32>) -> t...
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 11.5K bytes
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  4. tensorflow/compiler/mlir/tfr/examples/mnist/mnist_ops_test.py

        filter_ = tf.random.uniform([2, 2, 1, 8])
        bias = tf.zeros([8])
        kwargs = {
            'input_': input_,
            'filter_': filter_,
            'bias': bias,
            'stride_w': 2,
            'stride_h': 2,
            'dilation_w': 1,
            'dilation_h': 1,
            'padding': 'SAME',
            'act': 'RELU'
        }
    
        self._assertOpAndComposite([input_, filter_, bias],
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Sep 28 21:37:05 UTC 2021
    - 4K bytes
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  5. tensorflow/compiler/mlir/lite/experimental/tac/tests/target-annotation.mlir

      // CHECK: tac.device = "GPU", tac.inference_type = "FLOAT"
      %0 = "tfl.conv_2d"(%arg0, %arg1, %arg2) {dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 1 : i32, stride_w = 1 : i32} : (tensor<256x32x32x3xf32>, tensor<16x3x3x3xf32>, tensor<16xf32>) -> tensor<256x30x30x16xf32>
      func.return %0 : tensor<256x30x30x16xf32>
    }
    
    // -----
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri May 19 19:32:06 UTC 2023
    - 6.2K bytes
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  6. tensorflow/compiler/mlir/lite/tests/get-arithmetic-count.mlir

      // CHECK: _arithmetic_count = 230686720 : i64
      %0 = "tfl.conv_2d"(%arg0, %arg1, %arg2) {dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, padding = "SAME", stride_h = 1 : i32, stride_w = 1 : i32, fused_activation_function = "RELU6"} : (tensor<256x32x32x3xf32>, tensor<16x3x3x3xf32>, tensor<16xf32>) -> tensor<256x32x32x16xf32>
      func.return %0 : tensor<256x32x32x16xf32>
    }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Dec 14 04:58:17 UTC 2022
    - 7.7K bytes
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  7. tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/import_json.json

    // CHECK: %[[RES0:.*]] = "tfl.conv_2d"(%arg0, %arg1, %[[CST]]) <{dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, fused_activation_function = "NONE", padding = "SAME", stride_h = 1 : i32, stride_w = 1 : i32}> : (tensor<256x32x32x3xf32>, tensor<16x3x3x3xf32>, none) -> tensor<256x32x32x16xf32>
    // CHECK: return %[[RES0]] : tensor<256x32x32x16xf32>
    
    {
      "version": 3,
      "operator_codes": [
        {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 1.8K bytes
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  8. tensorflow/compiler/mlir/lite/tests/quantize-dynamic-range.mlir

      %dconv = "tfl.depthwise_conv_2d"(%arg0, %w, %b) {depth_multiplier = 4 : i32, dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 4 : i32, stride_w = 5 : i32} : (tensor<1x224x224x3xf32>, tensor<64x3x3x3xf32>, tensor<64xf32>)...
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 23 21:09:00 UTC 2024
    - 23.2K bytes
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  9. tensorflow/compiler/mlir/lite/experimental/tac/tests/get-op-cost.mlir

      // CHECK: tac.cost = 0x4D5C0000
      %0 = "tfl.conv_2d"(%arg0, %arg1, %arg2) {dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, padding = "SAME", stride_h = 1 : i32, stride_w = 1 : i32, fused_activation_function = "RELU6", tac.device = "CPU"} : (tensor<256x32x32x3xf32>, tensor<16x3x3x3xf32>, tensor<16xf32>) -> tensor<256x32x32x16xf32>
      func.return %0 : tensor<256x32x32x16xf32>
    }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Mar 24 05:29:10 UTC 2022
    - 5.7K bytes
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  10. tensorflow/compiler/mlir/lite/experimental/tac/tests/device-transform-nnapi.mlir

    // CHECK:           [[VAL_1:%.*]] = "tfl.average_pool_2d"([[VAL_0]]) <{filter_height = 48 : i32, filter_width = 48 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 1 : i32, stride_w = 1 : i32}> : (tensor<1x48x48x512xf32>) -> tensor<1x1x1x512xf32>
    // CHECK:           return [[VAL_1]] : tensor<1x1x1x512xf32>
    // CHECK:         }
    
    // -----
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 4.9K bytes
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