io64[2] = (io64[2] >> 4) & 0x0000FFFFFFFFFFFF
	// ppc64x: -"SRD", -"AND", "RLDICL\t[$]36, R[0-9]*, [$]28, R"
	io64[3] = (io64[3] >> 28) & 0x0000FFFFFFFFFFFF

	// ppc64x: "MOVWZ", "RLWNM\t[$]1, R[0-9]*, [$]28, [$]3, R"
	io64[4] = uint64(bits.RotateLeft32(io32[0], 1) & 0xF000000F)

	// ppc64x: "RLWNM\t[$]0, R[0-9]*, [$]4, [$]19, R"
	io32[0] = io32[0] & 0x0FFFF000

	BLT	next4
	MOVD	0(MASK_PTR), R14
	MOVD	0(BLK_INP), R15
	XOR	R14, R15, R14
	MOVD	R14, 0(BLK_OUT)
	ADD	$8, R16
	ADD	$-8, IN_LEN
next4:
	CMP	IN_LEN, $4
	BLT	next2
	MOVWZ	(BLK_INP)(R16), R15
	MOVWZ	(MASK_PTR)(R16), R14
	XOR	R14, R15, R14
	MOVW	R14, (R16)(BLK_OUT)
	ADD	$4, R16
	ADD	$-4, IN_LEN
next2:
	CMP	IN_LEN, $2
	BLT	next1
	MOVHZ	(BLK_INP)(R16), R15

#endif						\
	/* copy return values back */		\
	MOVD	regArgs+40(FP), R20;		\
	BL	runtime·spillArgs(SB);			\
	MOVD	stackArgsType+0(FP), R7;		\
	MOVD	stackArgs+16(FP), R3;			\
	MOVWZ	stackArgsSize+24(FP), R4;			\
	MOVWZ	stackRetOffset+28(FP), R6;		\
	ADD	$FIXED_FRAME, R1, R5;		\
	ADD	R6, R5; 			\
	ADD	R6, R3;				\
	SUB	R6, R4;				\
	BL	callRet<>(SB);			\
	RET

		{name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", typ: "Int64"},   // sign extend int32 to int64
		{name: "MOVWZreg", argLength: 1, reg: gp11, asm: "MOVWZ", typ: "Int64"}, // zero extend uint32 to uint64

		// Load bytes in the endian order of the arch from arg0+aux+auxint into a 64 bit register.

	MOVD	p_len+16(FP), LEN

	SRD	$6, LEN
	SLD	$6, LEN
	ADD	INP, LEN, END

	CMP	INP, END
	BEQ	end

	MOVD	$·kcon(SB), TBL_STRT
	MOVD	$0x10, R_x010

#ifdef GOARCH_ppc64le
	MOVWZ	$8, TEMP
	LVSL	(TEMP)(R0), LEMASK
	VSPLTISB	$0x0F, KI
	VXOR	KI, LEMASK, LEMASK
#endif

	LXVW4X	(CTX)(R_x000), V0
	LXVW4X	(CTX)(R_x010), V4

	// unpack the input values into vector registers

	MOVD	p_len+16(FP), LEN

	SRD	$6, LEN
	SLD	$6, LEN
	ADD	INP, LEN, END

	CMP	INP, END
	BEQ	end

	MOVD	$·kcon(SB), TBL_STRT
	MOVD	$0x10, R_x010

#ifdef GOARCH_ppc64le
	MOVWZ	$8, TEMP
	LVSL	(TEMP)(R0), LEMASK
	VSPLTISB	$0x0F, KI
	VXOR	KI, LEMASK, LEMASK
#endif

	LXVW4X	(CTX)(R_x000), V0
	LXVW4X	(CTX)(R_x010), V4

	// unpack the input values into vector registers

	l.restore()

	p("MOVD %d(R15), R14", l.stack)    // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
	p("ADD $%d, R15", l.stack+8)       // pop frame (including the space pushed by sigctxt.pushCall)
	p("MOVWZ -%d(R15), R10", l.stack)  // load flags to REGTMP
	p("TMLH R10, $(3<<12)")            // restore flags
	p("MOVD -%d(R15), R10", l.stack+8) // load PC to REGTMP
	p("JMP (R10)")
}

func genWasm() {

}

func TrailingZeros32(n uint32) int {
	// amd64/v1,amd64/v2:"BTSQ\\t\\$32","BSFQ"
	// amd64/v3:"TZCNTL"
	// 386:"BSFL"
	// arm:"CLZ"
	// arm64:"RBITW","CLZW"
	// s390x:"FLOGR","MOVWZ"
	// ppc64x/power8:"ANDN","POPCNTW"
	// ppc64x/power9: "CNTTZW"
	// wasm:"I64Ctz"
	return bits.TrailingZeros32(n)
}

func TrailingZeros16(n uint16) int {
	// amd64:"BSFL","ORL\\t\\$65536"

				src = 4
			case "MOVV", "MOVD":
				src = 8
			}
		case "s390x":
			switch op {
			case "MOVB", "MOVBZ":
				src = 1
			case "MOVH", "MOVHZ":
				src = 2
			case "MOVW", "MOVWZ", "FMOVS":
				src = 4
			case "MOVD", "FMOVD":
				src = 8
			}
		}
	}
	if dst == 0 {
		dst = src
	}

	// Determine whether the match we're holding
	// is the first or second argument.

				p.From.Sym = ctxt.Float64Sym(f64)
				p.From.Name = obj.NAME_EXTERN
				p.From.Offset = 0
			}
		}

	case AMOVW, AMOVWZ:
		// Note, for backwards compatibility, MOVW $const, Rx and MOVWZ $const, Rx are identical.
		if p.From.Type == obj.TYPE_CONST && p.From.Offset != 0 && p.From.Offset&0xFFFF == 0 {
			// This is a constant shifted 16 bits to the left, convert it to ADDIS/ORIS $const,...
			p.As = AADDIS