// arg2 = address of the last element of src
		// arg3 = mem
		// auxint = alignment
		// returns mem
		//	MOVx	(R20), Rtmp
		//	MOVx	Rtmp, (R21)
		//	ADDV	$sz, R20
		//	ADDV	$sz, R21
		//	BGEU	Rarg2, R20, -4(PC)
		{
			name:      "LoweredMove",
			aux:       "Int64",
			argLength: 4,
			reg: regInfo{
				inputs:   []regMask{buildReg("R21"), buildReg("R20"), gp},

(Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
(Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))

(Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c)
(Select1 <t> (Add64carry x y c)) =>
	(OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))

(Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c)
(Select1 <t> (Sub64borrow x y c)) =>
	(OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))

	MOVV	$1000, R6
	MULVU	R6, R7, R7
	MOVV	$1000000000, R6

	DIVVU	R6, R7, R5	// ts->tv_sec
	REMVU	R6, R7, R4	// ts->tv_nsec
	MOVV	R5, 8(R3)
	MOVV	R4, 16(R3)

	// nanosleep(&ts, 0)
	ADDV	$8, R3, R4
	MOVV	R0, R5
	MOVV	$SYS_nanosleep, R11
	SYSCALL
	RET

// func gettid() uint32
TEXT runtime·gettid(SB),NOSPLIT,$0-4
	MOVV	$SYS_gettid, R11
	SYSCALL
	MOVW	R4, ret+0(FP)
	RET

// Code generated by stringer -i a.out.go -o anames.go -p ppc64; DO NOT EDIT.

package ppc64

import "cmd/internal/obj"

var Anames = []string{
	obj.A_ARCHSPECIFIC: "ADD",
	"ADDCC",
	"ADDIS",
	"ADDV",
	"ADDVCC",
	"ADDC",
	"ADDCCC",
	"ADDCV",
	"ADDCVCC",
	"ADDME",
	"ADDMECC",
	"ADDMEVCC",
	"ADDMEV",
	"ADDE",
	"ADDECC",
	"ADDEVCC",
	"ADDEV",
	"ADDZE",
	"ADDZECC",
	"ADDZEVCC",
	"ADDZEV",

	mov := "MOVW"
	movf := "MOVF"
	add := "ADD"
	sub := "SUB"
	r28 := "R28"
	regsize := 4
	softfloat := "GOMIPS_softfloat"
	if _64bit {
		mov = "MOVV"
		movf = "MOVD"
		add = "ADDV"
		sub = "SUBV"
		r28 = "RSB"
		regsize = 8
		softfloat = "GOMIPS64_softfloat"
	}

	// Add integer registers R1-R22, R24-R25, R28
	// R0 (zero), R23 (REGTMP), R29 (SP), R30 (g), R31 (LR) are special,

			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.reset(OpLOONG64MULV)
		v.AddArg2(x, y)
		return true
	}
	// match: (Select0 <t> (Add64carry x y c))
	// result: (ADDV (ADDV <t> x y) c)
	for {
		t := v.Type
		if v_0.Op != OpAdd64carry {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.reset(OpLOONG64ADDV)

		v0 := b.NewValue0(v.Pos, OpMIPS64MULVU, types.NewTuple(typ.UInt64, typ.UInt64))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
	// match: (Select0 <t> (Add64carry x y c))
	// result: (ADDV (ADDV <t> x y) c)
	for {
		t := v.Type
		if v_0.Op != OpAdd64carry {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.reset(OpMIPS64ADDV)

	ADDE R3, R4                     // 7c841914
	ADDECC R3, R4                   // 7c841915
	ADDEV R3, R4                    // 7c841d14
	ADDEVCC R3, R4                  // 7c841d15
	ADDV R3, R4                     // 7c841e14
	ADDVCC R3, R4                   // 7c841e15
	ADDCCC R3, R4, R5               // 7ca41815
	ADDCCC $65536, R4, R5           // 641f0001600000007cbf2015

		name:           "DMB",
		auxType:        auxInt64,
		argLen:         1,
		hasSideEffects: true,
		asm:            arm64.ADMB,
		reg:            regInfo{},
	},

	{
		name:        "ADDV",
		argLen:      2,
		commutative: true,
		asm:         loong64.AADDVU,
		reg: regInfo{
			inputs: []inputInfo{