switch {
			case arch.IsARM64STLXR(op):
				// ARM64 instructions with one input and two outputs.
				prog.From = a[0]
				prog.To = a[1]
				if a[2].Type != obj.TYPE_REG {
					p.errorf("invalid addressing modes for third operand to %s instruction, must be register", op)
					return
				}
				prog.RegTo2 = a[2].Reg
			case arch.IsARM64TBL(op):
				// one of its inputs does not fit into prog.Reg.
				prog.From = a[0]

			"A",
			"B",
		),
		"THIS.\n",
	},
	{
		"nested #define with args",
		lines(
			"#define A #define B(x) x",
			"A",
			"B(THIS)",
		),
		"THIS.\n",
	},
	/* This one fails. See comment in Slice.Col.
	{
		"nested #define with args",
		lines(
			"#define A #define B (x) x",
			"A",
			"B(THIS)",
		),
		"x.\n",
	},
	*/
}

pkg syscall (linux-arm-cgo), const IFF_NOARP ideal-int
pkg syscall (linux-arm-cgo), const IFF_NOTRAILERS ideal-int
pkg syscall (linux-arm-cgo), const IFF_NO_PI ideal-int
pkg syscall (linux-arm-cgo), const IFF_ONE_QUEUE ideal-int
pkg syscall (linux-arm-cgo), const IFF_POINTOPOINT ideal-int
pkg syscall (linux-arm-cgo), const IFF_PORTSEL ideal-int
pkg syscall (linux-arm-cgo), const IFF_PROMISC ideal-int